ICS7151
Spread Spectrum Clock Generator
Description
The ICS7151-10, -20, -40, and -50 are clock
generators for EMI (Electro Magnetic Interference)
reduction (see below for frequency ranges and
multiplier ratios). Spectral peaks can be attenuated by
slightly modulating the oscillation frequency. Both down
and center spread profiles are selectable. Down spread
maintains an average frequency less than an unspread
clock, and will not exceed the maximum frequency of
an unspread clock.
Features
•
•
•
•
•
Operating voltage of 3.3 V ±0.3 V
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Input frequency range of 16.5 to 33.4 MHz
Output frequency ranges of 8.3 to 16.7 MHz, 16.5 to
33.4 MHz, 33.3 to 66.7 MHz, 66.6 to 133.4 MHz
±1.5% center spread; -1.0%, -3.0% down spread)
•
Provides a spread spectrum clock output (±0.5%,
•
Multiplication rates of x1/2, x1, x2, and x4
•
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
2
ENS
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
Clock Buffer/
Crystal
Ocsillator
CKOUT
XIN
XOUT
External caps required with crystal for
accurate tuning of the clock
GND
Product Lineup
Product
Input Frequency Range
Multiplier Ratio
Output Frequency Range
ICS7151M-10, ICS7151MI-10
ICS7151M-20, ICS7151MI-20
ICS7151M-40, ICS7151MI-40
ICS7151M-50, ICS7151MI-50
16.5 MHz to 33.4 MHz
16.5 MHz to 33.4 MHz
16.5 MHz to 33.4 MHz
16.5 MHz to 33.4 MHz
X1
X2
X4
X1/2
16.5 MHz to 33.4 MHz
33.3 MHz to 66.7 MHz
66.6 MHz to 133.4 MHz
8.3 MHz to 16.7 MHz
MDS 7151 E
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 012306
tel (408) 297-1201
●
www.icst.com
ICS7151
Spread Spectrum Clock Generator
Pin Assignment
XIN
GND
S0
S1
1
2
3
4
8
7
6
5
8 pin (150 mil) SOIC
XOUT
VDD
ENS
CKOUT
Spread Direction and Percentage
Select Table
S1
Pin 4
(note1)
0
0
1
1
ENS
(note 2)
S0
Pin 3
(note1)
0
1
0
1
Spread
Direction
Center
Center
Down
Down
Spread
Percentage (%)
±1.5
±0.5
-1.0
-3.0
Spread Spectrum
OFF
ON
0
1
Notes:
1. The modulation rate varies with input frequency.
2. Spread will default to ON when ENS pin is left open.
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
XIN
GND
S0
S1
CKOUT
ENS
VDD
XOUT
Input
Power
Input
Input
Output
Input
Power
Output
Resonator connection pin/clock input pin.
Connect to ground.
Select pin 0. Modulation rate setting pin.
Select pin 1. Modulation rate setting pin.
Modulated clock output pin.
Modulation enable setting pin. Internal pull-up resistor.
Connect to +3.3 V.
Resonator connection pin.
MDS 7151 E
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 012306
tel (408) 297-1201
●
www.icst.com
ICS7151
Spread Spectrum Clock Generator
External Components
The ICS7151 requires a minimum number of external
components for proper operation.
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. So,
for a crystal with a 16 pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between GND and VDD on pin 7, as close to this pin as
possible. For optimum device performance, the
decoupling capacitor should be mounted on the
component side of the PCB. Avoid the use of vias in the
decoupling circuit.
Series Termination Resistor
Series termination should be used on the clock output.
To series terminate a 50Ω trace (a commonly used
trace impedance) place a 27Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
25Ω.
Spread Spectrum Profile
The ICS7151 low EMI clock generator uses a triangular
frequency modulation profile for optimal down stream
tracking of zero delay buffers and other PLL devices.
The frequency modulation amplitude is constant with
variations of the input frequency.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI, the 27Ω series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS7151. This includes signal traces just
Modulation Rate
Frequency
Time
MDS 7151 E
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 012306
tel (408) 297-1201
●
www.icst.com
ICS7151
Spread Spectrum Clock Generator
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS7151. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs (referenced to GND)
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
Overshoot (V
IOVER
)
Undershoot (V
IUNDER
)
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85°C
-55 to +125°C
-40 to +125°C
260°C
VDD + 1.0 V (t
OVER
< 50 ns)
GND - 1.0 V (t
UNDER
< 50 ns)
Overshoot/Undershoot
t
UNDER
< 50 ns
V
IOVER
< V
DD
+ 1.0 V
V
DD
GND
V
IUNDER
< GND - 1.0 V
Input pin
t
OVER
< 50 ns
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.0
Typ.
3.3
Max.
+85
3.6
Units
°C
V
MDS 7151 E
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 012306
tel (408) 297-1201
●
www.icst.com
ICS7151
Spread Spectrum Clock Generator
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±0.3 V,
Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Supply Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
Symbol
VDD
IDD
V
IH
V
IL
V
OH
V
OL
C
IN
Conditions
No load, at 3.3 V
XIN, S0, S1, ENS
XIN, S0, S1, ENS
CKOUT, I
OH
= -4 mA
CKOUT, I
OL
= 4 mA
XIN, S0, S1, ENS
CKOUT, 8.3 to 66.7
MHz
Min.
3.0
VDDx0.8
0.0
2.0
Typ.
3.3
10
Max.
3.6
20
VDD + 0.3
VDDx0.20
0.4
16
15
10
7
Units
V
mA
V
V
V
V
pF
pF
pF
pF
kΩ
Load Capacitance
C
L
CKOUT, 66.7 to 100
MHz
CKOUT, 100 to 133.4
MHz
Input Pull-up Resistor
R
PU
ENS
100
240
400
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±0.3 V,
Ambient Temperature -40 to +85° C
Parameter
Input Crystal Frequency
Input Clock Frequency
Symbol
f
IN
Conditions
Min.
16.5
16.5
Typ.
Max.
33.4
33.4
33.4
66.7
133.4
16.7
Units
MHz
MHz
MHz
MHz
MHz
MHz
%
%
V/ns
CKOUT, Multiply by 1
(ICS7151-10)
CKOUT, Multiply by 2
(ICS7151-20)
CKOUT, Multiply by 4
(ICS7151-40)
CKOUT, 2-frequency
division (ICS7151-50)
Input Clock Duty Cycle
Output Clock Duty Cycle
Output Slew Rate
t
DCC
XIN, 16.5 to 33.4 MHz
CKOUT, 1.5 V
CKOUT, 0.4 to 2.4 V,
CL = 15 pF
16.5
33.3
66.6
8.3
40
40
0.5
50
Output Frequency
f
OUT
60
60
3.0
MDS 7151 E
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 012306
tel (408) 297-1201
●
www.icst.com
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
