SiHG73N60AEL
www.vishay.com
Vishay Siliconix
EL Series Power MOSFET
D
FEATURES
• Low figure-of-merit (FOM) R
on
x Q
g
• Low input capacitance (C
iss
)
• Reduced switching and conduction losses
TO-247AC
G
• Ultra low gate charge (Q
g
)
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
S
D
G
S
N-Channel MOSFET
APPLICATIONS
•
•
•
•
Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
PRODUCT SUMMARY
V
DS
(V) at T
J
max.
R
DS(on)
typ. () at 25 °C
Q
g
max. (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
342
34
57
Single
650
0.035
ORDERING INFORMATION
Package
Lead (Pb)-free and halogen-free
TO-247AC
SiHG73N60AEL-GE3
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current (T
J
= 150 °C)
Pulsed drain
Linear derating factor
Single pulse avalanche energy
b
Maximum power dissipation
Operating junction and storage temperature range
Reverse diode dv/dt
d
Soldering recommendations (peak temperature)
c
For 10 s
Notes
• Initial samples marked as SiHG73N60BE
a. Repetitive rating; pulse width limited by maximum junction temperature
b. V
DD
= 120 V, starting T
J
= 25 °C, L = 28.2 mH, R
g
= 25
,
I
AS
= 11 A
c. 1.6 mm from case
d. I
SD
I
D
, di/dt = 60 A/μs, starting T
J
= 25 °C
current
a
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J
, T
stg
dv/dt
LIMIT
600
± 30
69
44
206
4.2
1706
520
-55 to +150
3.2
260
UNIT
V
A
W/°C
mJ
W
°C
V/ns
°C
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum junction-to-ambient
Maximum junction-to-case (drain)
S18-0173-Rev. A, 12-Feb-18
SYMBOL
R
thJA
R
thJC
TYP.
-
-
MAX.
40
0.24
UNIT
°C/W
Document Number: 92068
1
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHG73N60AEL
www.vishay.com
Vishay Siliconix
SYMBOL
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
C
o(er)
V
DS
= 0 V to 480 V, V
GS
= 0 V
C
o(tr)
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
R
g
f = 1 MHz, open drain
MOSFET symbol
showing the
integral reverse
p - n junction diode
V
DD
= 480 V, I
D
= 36.5 A,
V
GS
= 10 V, R
g
= 10
V
GS
= 10 V
I
D
= 36.5 A, V
DS
= 480 V
-
-
-
-
-
-
-
-
0.3
888
171
34
57
51
80
244
104
0.7
-
342
-
-
102
160
488
208
1.5
ns
nC
TEST CONDITIONS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 20 V
V
GS
= ± 30 V
V
DS
= 600 V, V
GS
= 0 V
V
DS
= 480 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 36.5 A
V
DS
= 40 V, I
D
= 36.5 A
MIN.
600
-
2.0
-
-
-
-
-
-
-
-
-
-
TYP.
-
0.46
-
-
-
-
-
0.035
28
6709
282
7
181
MAX.
-
-
4.0
± 100
±1
1
100
0.042
-
-
-
-
pF
-
UNIT
V
V/°C
V
nA
μA
μA
S
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-source breakdown voltage
V
DS
temperature coefficient
Gate-source threshold voltage (N)
Gate-source leakage
Zero gate voltage drain current
Drain-source on-state resistance
Forward transconductance
a
Dynamic
Input capacitance
Output capacitance
Reverse transfer capacitance
Effective output capacitance, energy
related
a
Effective output capacitance, time
related
b
Total gate charge
Gate-source charge
Gate-drain charge
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate input resistance
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
D
V
GS
= 0 V,
V
DS
= 100 V,
f = 1 MHz
-
-
-
-
-
-
-
-
-
479
11
42
68
A
206
1.2
958
22
-
V
ns
μC
A
G
S
T
J
= 25 °C, I
S
= 36.5 A, V
GS
= 0 V
T
J
= 25 °C, I
F
= I
S
= 36.5 A,
di/dt = 100 A/μs, V
R
= 400 V
Notes
a. C
oss(er)
is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
b. C
oss(tr)
is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
S18-0173-Rev. A, 12-Feb-18
Document Number: 92068
2
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHG73N60AEL
www.vishay.com
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
250
TOP
Vishay Siliconix
3.0
R
DS(on)
, Drain-to-Source On-Resistance
(Normalized)
I
D
, Drain-to-Source Current (A)
200
150
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
T
J
= 25 °C
I
D
= 36.5 A
2.5
2.0
1.5
100
1.0
V
GS
= 10 V
0.5
50
0
0
10
15
V
DS
, Drain-to-Source Voltage (V)
5
20
0
-60 -40 -20
0 20 40 60 80 100 120 140 160
T
J
, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
100 000
150
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
T
J
= 150 °C
I
D
, Drain-to-Source Current (A)
120
10 000
C
iss
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
C, Capacitance (pF)
1000
C
oss
100
C
rss
90
60
10
30
1
0
0
10
15
V
DS
, Drain-to-Source Voltage (V)
5
20
0.1
0
100
200
300
400
500
V
DS
, Drain-to-Source Voltage (V)
600
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
250
T
J
= 25 °C
5000
40
35
30
25
C
oss
500
15
10
5
E
oss
20
I
D
, Drain-to-Source Current (A)
150
100
T
J
= 150 °C
50
V
DS
= 18 V
0
0
10
15
V
GS
,
Gate-to-Source
Voltage (V)
5
20
C
oss
, Output Capacitance (pF)
200
50
0
100
200
300
400
500
600
V
DS
, Drain-to-Source Voltage (V)
0
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - C
oss
and E
oss
vs. V
DS
S18-0173-Rev. A, 12-Feb-18
Document Number: 92068
3
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
E
oss
, Output Capacitance
Stored
Energy (μJ)
SiHG73N60AEL
www.vishay.com
Vishay Siliconix
80
12
V
DS
= 480 V
V
DS
= 300 V
V
DS
= 120 V
9
I
D
, Drain Current (A)
0
50
100
150
Q
g
, Total
Gate
Charge (nC)
200
V
GS
,
Gate-to-Source
Voltage (V)
60
6
40
3
20
0
0
25
50
75
100
125
T
C
, Case Temperature (°C)
150
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
800
V
DS
, Drain-to-Source Breakdown Voltage (V)
100
T
J
= 150 °C
775
750
725
700
675
650
625
I
D
= 10 mA
600
-60 -40 -20
0 20 40 60 80 100 120 140 160
T
J
, Junction Temperature (°C)
I
SD
, Reverse Drain Current (A)
10
1
T
J
= 25 °C
V
GS
= 0 V
0.1
0.2
0.4
0.6
0.8
1.0
V
SD
,
Source-Drain
Voltage (V)
1.2
1.4
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Operation in this area
Limited by R
DS(on)
100
Fig. 11 - Temperature vs. Drain-to-Source Voltage
I
DM
limited
I
D
, Drain Current (A)
10
Limited by R
DS(on)
*
100 μs
1 ms
1
10 ms
0.1
T
C
= 25
°C
T
J
= 150 °C
single
pulse
BVDSS limited
1
10
100
1000
V
DS
, Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is
specified
0.01
Fig. 9 - Maximum Safe Operating Area
S18-0173-Rev. A, 12-Feb-18
Document Number: 92068
4
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHG73N60AEL
www.vishay.com
Vishay Siliconix
1
Duty cycle = 0.5
Normalized Effective Transient
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single
pulse
0.01
0.0001
0.001
0.01
Pulse Time (s)
0.1
1
Fig. 12 - Normalized Transient Thermal Impedance, Junction-to-Case
V
DS
V
GS
R
g
R
D
t
p
D.U.T.
+
- V
DD
V
DS
V
DS
V
DD
10 V
Pulse width ≤ 1 μs
Duty factor ≤ 0.1 %
I
AS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
V
DS
90 %
10 V
Q
gs
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gd
V
G
Fig. 14 - Switching Time Waveforms
L
V
DS
Vary t
p
to obtain
required I
AS
Charge
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same
type as D.U.T.
50 kΩ
12 V
0.2 μF
0.3 μF
R
g
D.U.T.
I
AS
+
- V
DD
+
D.U.T.
0.01
Ω
V
GS
3 mA
-
V
DS
10 V
t
p
Fig. 15 - Unclamped Inductive Test Circuit
I
G
I
D
Current
sampling
resistors
Fig. 18 - Gate Charge Test Circuit
S18-0173-Rev. A, 12-Feb-18
Document Number: 92068
5
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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