ICS556-01
B
ROADCOM
25 MH
Z
LVDS C
LOCK
Description
The ICS556-01 is a clock oscillator with LVDS outputs.
Using a standard 25 MHz crystal, the device outputs a
.25 mHz (reference) differential output clock. The
operation voltage is 2.5 V to support today’s popular
interfaces. The termination resistor is off-chip.
Features
•
•
•
•
•
•
Packaged in 8-pin TSSOP
Requires no external components
Low Phase Jitter: <1 ps from 10 kHz to 10 MHz
Differential LVDS outputs
Operating voltage of 2.5 V.
Advanced, low power, sub-micron CMOS process
Block Diagram
VDD
OE
X1
25 MHz Crystal
X2
Crystal
Oscillator
CLK
100
CLK
2
GND
MDS 556-01 B
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
●
Revision 020204
te l (40 8) 2 97-12 01
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ICS556-01
Broadcom 25 MHz LVDS Clock
Pin Assignment
X1
VDD
GND
GND
1
2
3
4
8
7
6
5
X2
OE
CLK
CLK
ICS556-01
8 Pin (173m il) TSSO P or SO IC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1
VDD
GND
GND
CLK
CLK
OE
X2
Pin
Type
Input
Power
Power
Power
Output
Power
Input
Input
Crystal connection.
Pin Description
Power supply. Connect to 2.5 V.
Connect to ground.
Connect to ground.
Inverting differential clock output.
Differential clock output.
Output Enable. Internal pull-up resistor.
Crystal connection.
only partial outputs are used, it is recommended to
terminate the un-used outputs.
External Component Selection
The ICS556-01 requires a minimum number of external
components for proper operation. A 100Ω termination
resistor between CLK and CLK is provided on-chip.
2.5V
LVDS_Driver
2.5V
+
-
Decoupling Capacitors
A decoupling capacitor of 0.01µF should be connected
between VDD and GND on pins 2 and 3 as close to the
ICS556-01 as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
R1
100 ohm
100 Ohm Differential Transmission Line
LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100
differential transmission line environment, LVDS drivers
require a matched load termination of 100 across near
the receiver input. For a multiple LVDS outputs buffer, if
FIGURE 2. TYPICAL LVDS
DRIVER TERMINATION
MDS 556-01 B
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 020204
tel (4 08) 297-1 201
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ICS556-01
Broadcom 25 MHz LVDS Clock
Quartz Crystal
The ICS556-01 25 MHz LVDS Clock utilizes an
external crystal to generate a low phase noise output.
To assure the best system performance and reliability,
a crystal device with the recommended parameters
(shown below) must be used, and the layout guidelines
discussed in the following section shown must be
followed.
The frequency of oscillation of a quartz crystal is
determined by its “cut” and by the load capacitors
connected to it. The crystal specified for use with the
ICS556-01 is designed to have zero frequency error
when the total of on-chip plus stray capacitance is 5 pF.
Recommended Crystal Parameters:
Initial Accuracy of 25
°
C
±
20 ppm
Temperature Stability
±
20 ppm
Load Capacitance5 pf
Shunt Capacitance, C02 pF Max
Equivalent Series Resistance80
Ω
Max
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the ICS556-01. There should be no via’s
between the crystal pins and the X1 and X2 device
pins. There should be no signal traces underneath or
close to the crystal.
The value (in pF) of these crystal caps should equal
(C
L
- 12 pF)*2. In this equation, C
L
=crystal load
capacitance in pF. Example: or a crystal with a 16 pF
load capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS556-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70°C
-65 to +150°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
Min.
0
+2.375
Typ.
Max.
+70
+2.625
Units
°C
V
Refer to page 3
MDS 556-01 B
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 020204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS556-01
Broadcom 25 MHz LVDS Clock
DC Electrical Characteristics
VDD=2.5 V ±5%
, Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Symbol
VDD
V
OH
V
OL
V
OH
IDD
Conditions
Note 1
Note 1
I
OH
= -4 mA
No load, OE = 1
No load, OE = 0
Min.
2.375
1.375
Typ.
Max.
2.625
1.125
Units
V
V
V
V
VDD-0.4
5.3
1.7
mA
mA
Note 1: Outputs terminated with 50Ω to VDD/2
AC Electrical Characteristics
VDD = 2.5 V ±5%,
Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Frequency
Output Frequency
Differential Output Voltages (V
OD
)
∆
V
OD
Offset Voltage (V
OS
)
∆
V
OS
Differential Output Short Circuit Current (I
OSD
)
Output Short Circuit Current (I
OS
)
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Maximum Output Jitter (p-p)
Phase Jitter (RMS)
Conditions
Min.
Typ.
25
25
Max. Units
MHz
MHz
450
40
1.375
25
mV
mV
V
mV
mA
mA
1.2
1.2
55
ns
ns
%
ps
2.5
ps
250
V
OD
Magnitude Change
V
OS
Magnitude Change
-40
1.125
350
0
1.25
3
-3.5
-3.5
20% to 80%, no load
20% to 80%, no load
Measured at 1.25 V,
C
L
=5 pF
C
L
=5 pF
Phase Noise integrated
from 10 kHz to 10 MHz
45
0.8
0.8
50
40
1.8
MDS 556-01 B
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 020204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
ICS556-01
Broadcom 25 MHz LVDS Clock
Parameter Measurement Information
V
DD
= 2.5V±5%
Z = 50
Ω
SCOPE
Qx
50
Ω
LVDS
Z = 50
Ω
nQx
80%
80%
V
OD
50
Ω
Clock
Outputs
20%
t
OR
t
OF
20%
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
R
ISE
/F
ALL
T
IME
V
DD
nCLK
LV D S
out
D C In p u t
50
Ω
50
Ω
out
CLK
Pulse Width
V
O S
/
∆
V
O S
t
PERIOD
V
OS
S
ETUP
t
PW
& t
PERIOD
V
DD
nCLK
V
OH
out
CLK
t(
φ
)
V
OL
DC Input
LVDS
100
Ω
V
OD
/
∆
V
OD
out
t
jit(
φ
) =
t
(
φ
) -
t
(
φ
)
mean
= Phase Jitter
P
HASE
J
ITTER
V
OD
S
ETUP
VDD
nCLK
CLK
VOD
Cross Points
VOS
GND
D
IFFERENTIAL
I
NPUT
L
EVEL
MDS 556-01 B
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 020204
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
嵌入式系统
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