PLL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
FEATURES
•
•
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 700MHz (4x
multiplier), or 800MHz – 1GHz (LVDS output
only for 8x multiplier).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DIE CONFIGURATION
65 mil
OUTSEL0^
OUTSEL1^
SEL0^
SEL1^
VDD
VDD
VDD
VDD
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
CMOS
LVDSB
PECLB
VDDBUF
VDDBUF
PECL
LVDS
OE_SEL^
•
•
•
•
•
•
XIN
XOUT
SEL3^
62 mil
26
27
Die ID:
A1919-19A
15
28
14
13
SEL2^
OE
CTRL
VCON
29
12
11
30
DESCRIPTION
PLL520-00 is a VCXO IC specifically designed to
pull high frequency fundamental crystals. Its design
was optimized to tolerate higher limits of
interelectrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. Its internal varicaps allow an on chip
frequency pulling, controlled by the VCON input.
C502A
31
1
2
3
4
5
6
7
8
10
9
Y
(0,0)
X
Note: ^ denotes internal pull up
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OE_SELECT
(Pad #9)
0
OUTSEL0
(Pad #25)
0
1
0
1
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
State
Tri-state
Output enabled
Output enabled
Tri-state
BLOCK DIAGRAM
SEL
OE
VCON
Oscillator
Amplifier
w/
XIN
integrated
varicaps
PLL
(Phase
Locked
Loop)
Q
Q
XOUT
PLL by-pass
PLL520-00
1 (Default)
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
65 x 62 mil
GND
80 micron x 80 micron
10 mil
Pad #9, 18, 25: Bond to GND to set to “0”. No connection results to
“default” setting through internal pull-up.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “1”
Logical states defined by CMOS levels if OE_SELECT is “0
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1
GNDBUF
GND
GND
GND
GND
GND
NC
GND
PLL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
FREQUENCY SELECTION TABLE
Pad #28
SEL3
0
1
1
1
Pad #29
SEL2
0
0
1
1
Pad #19
SEL1
1
1
1
1
Pad #20
SEL0
1
1
0
1
Selected Multiplier
Fin x 8 (LVDS ouputs only)
Fin x 4
Fin x 2
No multiplication (no PLL)
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Interelectrode Capacitance
Crystal Pullability
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
C
0
/C
1 (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
Die at VCON = 1.65V
AT cut
AT cut
MIN.
100
TYP.
4
MAX.
200
3.5
250
30
UNITS
MHz
pF
pF
-
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 2
PLL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
On-chip Varicaps control range
Linearity
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 100 – 200MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
VCON = 0 to 3.3V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
pF
%
ppm/V
kΩ
kHz
200*
±100*
4 – 18*
10*
65
60
0V
≤
VCON
≤
3.3V, -3dB
25
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
Supply Current (Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
PECL/LVDS/CMOS
@ 50% V
DD
(CMOS)
@ 1.25V (LVDS)
@ V
DD
– 1.3V (PECL)
MIN.
2.97
45
45
45
TYP.
MAX.
100/80/40
3.63
55
55
55
UNITS
mA
V
%
mA
50
50
50
±50
5. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-
peak
Random Jitter
Integrated jitter RMS at
155MHz
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-
peak
Random Jitter
Integrated jitter RMS at
622MHz
Measured on Wavecrest SIA 3000
CONDITIONS
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
18.5
2.5
24
2.5
0.3
11
45
11
24
3
1.6
MAX.
20
27
UNITS
ps
ps
ps
0.4
49
27
ps
ps
ps
ps
1.8
ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 3
PLL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
6. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
FREQUENCY
155.52MHz
622.08MHz
@10Hz
-75
-75
@100Hz
-95
-95
@1kHz
-125
-110
@10kHz
-140
-125
@100kHz
-145
-120
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Electrical Characteristics
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
I
OH
I
OL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP.
MAX.
UNITS
mA
mA
mA
mA
2.4
1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 4
PLL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
8. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
9. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 5
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