PLL502-39U
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FEATURES
•
•
•
•
•
•
•
•
•
Selectable 750kHz to 800MHz range.
Low phase noise output (@ 10kHz frequency
offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz).
12 to 25MHz crystal input.
No external load capacitor or varicap required.
Inverted LVDS signal Output Enable selector.
Wide pull range (+/-200 ppm)
Selectable 1/16 to 32x frequency multiplier.
3.3V operation.
Available in 16-Pin (TSSOP or 3x3mm QFN).
PIN CONFIGURATION
(Top View)
SEL0^
10
XOUT
SEL3^
SEL2^
OE
13
14
15
16
12
11
SEL1^
9
XIN
VDD
8
7
6
5
GND
CLKC
VDD
CLKT
PLL502-39U
1
2
3
4
DESCRIPTION
VCON
GND
GND
The PLL502-39U (LVDS) is a high performance and
low phase noise VCXO clock IC. It provides phase
noise performance as low as –125dBc at 10kHz off-
set (at 155MHz), by multiplying the input crystal fre-
quency up to 32x. The wide pull range (+/- 200 ppm)
and very low jitter makes this ideal for a wide range
of applications, including SONET/SDH and FEC.
PLL502-39 accepts fundamental parallel resonant
mode crystals input from 12 to 25MHz.
Note: ^ designates Internal pull-up
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL502-39U
OE
1
0 (Default)
Tri-state
GND
State
Output enabled
BLOCK DIAGRAM
SEL
OE
VCON
Oscillator
XIN
XOUT
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
CLKC
CLKT
PLL by-pass
PLL502-39U
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/29/05 Page 1
PLL502-39U
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
FREQUENCY SELECTION TABLE
SEL3
0
0
0
1
1
1
1
1
1
1
SEL2
0
1
1
0
0
0
1
1
1
1
SEL1
1
1
1
0
1
1
0
0
1
1
SEL0
1
0
1
1
0
1
0
1
0
1
Selected Multiplier
Fin x 32
Fin / 8
Fin x 2
Fin / 2
Fin / 16
Fin x 4
Fin / 4
Fin x 8
Fin x 16
No multiplication
PIN DESCRIPTIONS
Name
VCON
GND
CLKT
VDD
CLKC
SEL1
SEL0
VDD
XIN
XOUT
SEL3
SEL2
OE
3x3mm QFN
Pin number
1
2,3,4,8
5
6
7
9
10
11
12
13
14
15
16
Type
I
P
O
P
O
I
I
P
I
I
I
I
I
Voltage Control input.
Ground connection.
LVDS Output
+3.3V power supply.
Complementary LVDS output
Multiplier selector pins. These pins have an internal pull-up that will
default SEL to ‘1’ when not connected to GND.
+3.3V power supply.
Crystal input. See Crystal Specification on page 3.
Crystal output. See Crystal Specification on page 3.
Multiplier selector pins. These pins have an internal pull-up that will
default SEL to ‘1’ when not connected to GND.
Output enable pin (see OE logic state table on page 1).
Description
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/29/05 Page 2
PLL502-39U
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Crystal Pullability
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
C
0
/C
1 (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
At VCON = 1.65V
AT cut
AT cut
MIN.
12
TYP.
9.5
MAX.
25
250
30
UNITS
MHz
pF
-
Ω
Note:
Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at
nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This how-
ever may reduce the pull range.
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
VCON pin input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 12 – 25MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
ppm/V
%
kΩ
kHz
500
±200
150
10
2000
25
0V
≤
VCON
≤
3.3V, -3dB
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/29/05 Page 3
PLL502-39U
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
4. General Electrical Specifications
PARAMETERS
Supply Current,
Dynamic (with
Loaded Outputs)
Operating Voltage
Output Clock
Duty Cycle
Short Circuit
Current
SYMBOL
I
DD
V
DD
@ 1.25V
CONDITIONS
Fout<24MHz
24MHz<Fout<96MHz
96MHz<Fout<800MHz
MIN.
TYP.
MAX.
25
45
80
3.63
UNITS
mA
V
%
mA
2.97
4
50
±50
55
5. Jitter Specifications
PARAMETERS
CONDITIONS
With capacitive decoupling be-
tween VDD and GND.
Over 10,000 cycles.
FREQUENCY
19.44MHz
77.76MHz
155.52MHz
622.08MHz
19.44MHz
77.76MHz
155.52MHz
622.08MHz
155.52MHz
622.08MHz
MIN.
TYP.
2.2
4.5
4.5
5.0
17
25
27
35
2.5
2.5
MAX.
UNITS
Period jitter RMS
ps
Period jitter Peak-to-
Peak
1
With capacitive decoupling be-
tween VDD and GND.
Over 10,000 cycles.
Integrated 12 kHz to 20 MHz
ps
Integrated jitter RMS
4
4
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
(typical)
FREQUENCY
19.44MHz
77.76MHz
155.52MHz
622.08MHz
@10Hz
-80
-72
-65
-55
@100Hz
-108
-103
-95
-85
@1kHz
-132
-122
-120
-109
@10kHz
-142
-130
-125
-115
@100kHz
-150
-125
-121
-110
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/29/05 Page 4
PLL502-39U
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise IC’s
8. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
MAX.
454
50
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
1.4
0.9
1.125
0
1.1
1.2
3
±1
-5.7
1.6
1.375
25
±10
-8
V
out
= V
DD
or GND
V
DD
= 0V
9. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
C
L
= 10 pF
(see figure)
R
L
= 100
Ω
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/29/05 Page 5
嵌入式系统
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