PLL502-26
High Pull-Range VCXO (27MHz) with integrated Audio PLL
FEATURES
•
•
•
•
•
•
•
•
•
•
Low phase noise 27MHz VCXO (-135 dBc at
10kHz offset).
Integrated variable capacitors.
Wide pull range (+/- 250 ppm).
Low jitter (RMS): 10ps period.
Integrated audio Phase Locked Loop.
Audio clock output (ideal for 8.192MHz,
11.2896MHz, 12.288MHz).
27MHz crystal input.
Audio Reference clock input.
3.3V operation.
Available in 16-Pin SOIC.
PIN CONFIGURATION
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9
N/C*
VDD_PLL
VDD_VCXO
XIN
XOUT
VCON
GND_VCXO
GND_PLL
1
2
N/C*
GND_27MHz
OUT_27MHz
VDD_27MHz
VDD_Audio
OUT_Audio
GND_Audio
REF_Audio
PLL502-26
3
4
5
6
7
8
DESCRIPTION
The PLL502-26 is a low cost, high pull-range and
low phase noise VCXO, providing less than -135dBc
at 10kHz offset at 27MHz. It also integrates an Audio
clock phase locked loop ideal for the 8.192MHz,
11.2896MHz and 12.288MHz audio outputs, starting
from an audio reference clock. Its very high pull
range makes it ideal for Digital Video applications,
allowing users to save board space and cost.
Note: *
Pins reserved for future DAC integration
OUTPUT RANGE
OUTPUT
VCXO
Audio
FREQUENCY RANGE
27MHz
8.192MHz – 12.288MHz
OUTPUT
TYPE
CMOS
CMOS
BLOCK DIAGRAM
VCON
XIN
XOUT
VARICAP
XTAL
OSC
OUT_27MHz
REF_Audio
10X
PLL
OUT_Audio
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 1
PLL502-26
High Pull-Range VCXO (27MHz) with integrated Audio PLL
PIN DESCRIPTIONS
Name
N/C
VDD_PLL
VDD_VCXO
XIN
XOUT
VCON
GND_VCXO
GND_PLL
REF_Audio
GND_Audio
OUT_Audio
VDD_Audio
VDD_27MHz
OUT_27MHz
GND_27MHz
Number
1,16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Type
No connection.
P
P
I
O
I
P
P
I
P
O
P
P
O
P
Description
VDD power supply pin for PLL circuitry. This pin should be decoupled sepa-
rately from other VDD.
VDD power supply pin for VCXO circuitry. This pin should be decoupled
separately from other VDD.
Crystal input. See Crystal Specifications on page 4.
Crystal output. See Crystal Specifications on page 4.
Voltage Control input.
GND connection for VCXO circuitry.
GND connection for VCXO circuitry.
Audio Reference Clock input.
GND connection for Audio clock output buffer circuitry.
Audio clock output.
VDD power supply pin for Audio clock output buffer. This pin should be
decoupled separately from other VDD.
VDD power supply pin for 27MHz output clock. This pin should be decoup-
led separately from other VDD.
27MHz VCXO output clock.
GND connection for 27MHz output buffer circuitry.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 2
PLL502-26
High Pull-Range VCXO (27MHz) with integrated Audio PLL
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Audio Reference Clock
Output Clock Rise/Fall Time
Output Clock Duty Cycle
SYMBOL
REF_Audio
CONDITIONS
MIN.
0.65
TYP.
27
-
2
50
MAX.
1.5
55
UNITS
MHz
MHz
ns
%
0.3V ~ 3.0V with 15 pF load
Measured @ 50% V
DD
45
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
VCXO Tuning Characteristic
Pull range linearity
VCON pin input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 12 – 27MHz;
XTAL C
0
/C
1
< 250
0V
≤
VIN
≤
3.3V
VCON=1.65V
±1.65V
MIN.
TYP.
10
500
MAX.
UNITS
ms
ppm
ppm
ppm/V
%
kΩ
kHz
±250
150
10
2000
25
0V
≤
VIN
≤
3.3V, -3dB
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. Jitter and Phase Noise Specification
PARAMETERS
RMS Period Jitter
(1 sigma – 10,000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
with capacitive decoupling
between VDD and GND.
27MHz @100Hz offset
27MHz @1kHz offset
27MHz @10kHz offset
27MHz @100kHz offset
27MHz @1MHz offset
MIN.
TYP.
3
-85
-115
-135
-140
-150
MAX.
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 3
PLL502-26
High Pull-Range VCXO (27MHz) with integrated Audio PLL
5. DC Specification
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
Operating Voltage
Output drive current
Short Circuit Current
VCXO Control Voltage
SYMBOL
I
DD
V
DD
I
OH
I
OL
VCON
CONDITIONS
F
XIN
= 12 - 27MHz
Ouput load of 10pF
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
MIN.
TYP.
30
MAX.
35
3.63
UNITS
mA
V
mA
mA
mA
V
2.97
10
10
±50
0
3.3
6. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Capacitance Rating
C0/C1
ESR
SYMBOL
F
XIN
C
L
(xtal)
R
S
MIN.
TYP.
27
9.5
MAX.
UNITS
MHz
pF
-
Ω
250
30
Note:
Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at
nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally.
This however may reduce the pull range.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 4
PLL502-26
High Pull-Range VCXO (27MHz) with integrated Audio PLL
PACKAGE INFORMATION
16 PIN Narrow SOIC ( mm )
SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.35
0.10
0.33
0.19
9.80
3.80
5.80
0.40
1.27 BSC
Max.
1.75
0.25
0.51
0.25
10.00
4.00
6.20
1.27
A1
B
A
C
L
e
D
E
H
ORDERING INFORMATION
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL502-26 S C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
PACKAGE TYPE
S=SOIC
Order Number
PLL502-26SC
PLL502-26SC-R
Marking
P502-26SC
P502-26SC
Package
t
SOIC - Tube
SOIC (Tape & Reel)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/17/04 Page 5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
