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INDEX

PRELIMINARY

MX29F1611

16M-BIT [2M x 8/1M x 16] CMOS

SINGLE VOLTAGE PAGEMODE FLASH EEPROM

FEATURES

•

5V

±

5% write, erase and read

JEDEC-standard EEPROM commands

Endurance: 10,000 cycles

Fast access time: 100/120/150ns

Fast pagemode access time: 50/60/70ns

Page access depth: 16 bytes/8 words, page address

A0, A1, A2

• Sector erase architecture

- 16 equal sectors of 128k bytes each

- Sector erase time: 150ms typical

• Auto Erase and Auto Program Algorithms

- Automatically erases any one of the sectors or the

whole chip with Erase Suspend capability

- Automatically programs and verifies data at

specified addresses

• Status Register feature for detection of program or

erase cycle completion

• Low VCC write inhibit is equal to or less than 3.2V

• Software and hardware data protection

• Page program operation

- Internal address and data latches for 128 bytes/64

words per page

- Page programming time: 5ms typical

- Byte programming time: 39us in average

• Low power dissipation

- 80mA active current

- 100uA standby current

• CMOS inputs and outputs

• Two independently Protected sectors

• Industry standard surface mount packaging

- 44 lead SOP

GENERAL DESCRIPTION

The MX29F1611 is a 16-mega bit Pagemode Flash

memory organized as either 1M wordx16 or 2M bytex8.

The MX29F1611 includes 16-128KB(131,072 Bytes)

blocks or 16-64KW(65,536 Words)blocks. MXIC's Flash

memories offer the most cost-effective and reliable read/

write non-volatile random access memory and fast page

mode access. The MX29F1611 is packaged 44-pin

SOP. It is designed to be reprogrammed and erased in-

system or in-standard EPROM programmers.

The standard MX29F1611 offers access times as fast as

100ns,allowing operation of high-speed microprocessors

without wait. To eliminate bus contention, the

MX29F1611 has separate chip enable CE, output enable

(OE), and write enable (WE) controls.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F1611 uses a command register to manage this

functionality.

To allow for simple in-system reprogrammability, the

MX29F1611 does not require high input voltages for

programming. Five-volt-only commands determine the

operation of the device. Reading data out of the device

is similar to reading from an EPROM.

MXIC Flash technology reliably stores memory contents

even after 10,000 cycles. The MXIC's cell is designed to

optimize the erase and programming mechanisms. In

addition, the combination of advanced tunnel oxide

processing and low internal electric fields for erase and

programming operations produces reliable cycling. The

MX29F1611 uses a 5V

±

5% VCC supply to perform the

Auto Erase and Auto Program algorithms.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up

protection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC +1V.

P/N: PM0440

1

REV. 1.6, JUL. 16, 1998

INDEX

MX29F1611

PIN CONFIGURATIONS

44 SOP(500mil)

WE

A18

A17

A7

A6

A5

A4

A3

A2

A1

A0

CE

GND

OE

Q0

Q8

Q1

Q9

Q2

Q10

Q3

Q11

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

WP

A19

A8

A9

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

PIN DESCRIPTION

SYMBOL

A0 - A19

Q0 - Q14

Q15/A - 1

CE

OE

WE

WP

BYTE

VCC

GND

PIN NAME

Address Input

Data Input/Output

Q15(Word mode)/LSB addr.(Byte mode)

Chip Enable Input

Output Enable Input

Write Enable Input

Sector Write Protect Input

Word/Byte Selection Input

Power Supply

Ground Pin

MX29F1611

P/N: PM0440

REV. 1.6, JUL. 16, 1998

2

INDEX

MX29F1611

BLOCK DIAGRAM

WE

OE

WP

PWD

BYTE

CONTROL

INPUT

LOGIC

PROGRAM/ERASE

HIGH VOLTAGE

WRITE

STATE

MACHINE

(WSM)

COMMAND INTERFACE

REGISTER

X-DECODER

MX29F1611

FLASH

ARRAY

SOURCE

HV

Y-PASS GATE

(CIR)

ADDRESS

LATCH

Q15/A-1

A0-A19

AND

BUFFER

COMMAND

DATA

DECODER

Y-DECODER

SENSE

AMPLIFIER

Y-SELECT

PGM

DATA

HV

COMMAND

DATA LATCH

PAGE

PROGRAM

DATA LATCH

Q0-Q15/A-1

I/O BUFFER

P/N: PM0440

REV. 1.6, JUL. 16, 1998

3

INDEX

MX29F1611

Table1.PIN DESCRIPTIONS

SYMBOL

A0 - A19

TYPE

INPUT

NAME AND FUNCTION

ADDRESS INPUTS: for memory addresses. Addresses are internally latched

during a write cycle.

LOW-BYTE DATA BUS: Input data and commands during Command Interface

Register(CIR) write cycles. Outputs array,status and identifier data in the

appropriate read mode. Floated when the chip is de-selected or the outputs are

disabled.

HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations. Outputs

array, identifier data in the appropriate read mode; not used for status register

reads. Floated when the chip is de-selected or the outputs are disabled

Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB

ADDRESS(BYTE = LOW)

CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,

decoders and sense amplifiers. With CE high, the device is deselected and

power consumption reduces to Standby level upon completion of any current

program or erase operations. CE must be low to select the device.

OUTPUT ENABLES: Gates the device's data through the output buffers during

a read cycle OE is active low.

WRITE ENABLE: Controls writes to the Command Interface Register(CIR). WE

is active low.

WRITE PROTECT: Top or Bottom sector can be protected by writing a non-

volatile protect-bit for each sector. When WP is high, all sectors can be

programmed or erased regardless of the state of the protect-bits. The WP input

buffer is disabled when PWD transitions low(deep power-down mode).

BYTE ENABLE: BYTE Low places device in x8 mode. All data is then input or

output on Q0-7 and Q8-14 float. AddressQ15/A-1 selects between the high and

low byte. BYTE high places the device in x16 mode, and turns off the Q15/A-1

input buffer. Address A0, then becomes the lowest order address.

DEVICE POWER SUPPLY(5V± 5%)

GROUND

Q0 - Q7

INPUT/OUTPUT

Q8 - Q14

INPUT/OUTPUT

.

Q15/A -1

INPUT/OUTPUT

CE

INPUT

OE

INPUT

WE

INPUT

WP

INPUT

BYTE

INPUT

VCC

GND

P/N: PM0440

REV. 1.6, JUL. 16, 1998

4

INDEX

MX29F1611

BUS OPERATION

Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory conform

to standard microprocessor bus cycles.

Table 2.1 Bus Operations for Word-Wide Mode (BYTE = VIH)

Mode

Read

OutputDisable

Standby

DeepPower-Down

Notes

1

2,4

1,3

CE

VIL

VIH

X

VIL

OE

VIL

VIH

X

VIL

VIH

WE

VIH

X

VIH

VIL

A0

X

VIL

VIH

X

A1

X

VIL

X

A9

X

VID

X

Q0-Q7

DOUT

HighZ

C2H

F7H

DIN

Q8-Q14

DOUT

HighZ

HIghZ

HighZ

00H

DIN

Q15/A-1

DOUT

HighZ

0B

DIN

ManufacturerID

DeviceID

Write

Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)

Mode

Read

OutputDisable

Standby

DeepPower-Down

Notes

1

2,4

1,3

CE

VIL

VIH

X

VIL

OE

VIL

VIH

X

VIL

VIH

WE

VIH

X

VIH

VIL

A0

X

VIL

VIH

X

A1

X

VIL

X

A9

X

VID

X

Q0-Q7

DOUT

HighZ

C2H

F7H

DIN

Q8-Q14

DOUT

HighZ

HIghZ

HighZ

Q15/A-1

VIL/VIH

X

VIL

VIL/VIH

ManufacturerID

DeviceID

Write

NOTES :

1.X can be VIH or VIL for address or control pins.

2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and with appropriate

sector addresses provide Sector Protect Code.(Refer to Table 4)

3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully completed through

proper command sequence.

4. VID = 11.5V- 12.5V.

5. Q15/A-1 = VIL, Q0 - Q7 =D0-D7 out . Q15/A-1 = VIH, Q0 - Q7 = D8 -D15 out.

P/N: PM0440

REV. 1.6, JUL. 16, 1998

5

MX29F1611

MX29F1611概述

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