19-1996; Rev 1; 12/01
N KIT
LUATIO
EVA
BLE
AVAILA
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
General Description
Features
o
Single +3.3V Supply
o
530mW Operating Power
o
Fully Integrated Clock Recovery and Data
Retiming
o
Exceeds ANSI, ITU, and Bellcore Specifications
o
Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
o
2.488Gbps Serial to 155Mbps Parallel Conversion
o
Differential PECL Clock Output
o
Single-Ended PECL Data Outputs
o
Tolerates >2000 Consecutive Identical Digits
o
Loss-of-Lock Indicator
MAX3881
The MAX3881 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers sin-
gle-ended PECL parallel data outputs and a differential
PECL parallel clock output for interfacing with digital
circuitry.
The MAX3881 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3881’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor.
The MAX3881 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP package.
Ordering Information
PART
MAX3881ECB
*Exposed
pad
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
64 TQFP-EP*
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
TOP VIEW
PD15
PD14
GND
GND
LOL
V
CC
V
CC
Pin Configuration
PD13
PD12
PD11
GND
GND
V
CC
V
CC
V
CC
V
CC
64
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND
FIL+
FIL-
V
CC
PHADJ+
PHADJ-
V
CC
SDI+
SDI-
V
CC
SLBI+
SLBI-
V
CC
SIS
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
V
CC
PD10
V
CC
PD9
V
CC
PD8
V
CC
GND
V
CC
PD7
V
CC
PD6
V
CC
PD5
V
CC
GND
Typical Application Circuit appears at end of data sheet.
MAX3881
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PD1
PD2
PD4
V
CC
V
CC
V
CC
PCLK+
PCLK-
GND
PD0
GND
TQFP-EP*
*EXPOSED PAD IS CONNECTED TO GND.
________________________________________________________________
Maxim Integrated Products
PD3
V
CC
V
CC
V
CC
V
CC
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
MAX3881
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V
CC
)...............................-0.5V to +7.0V
Input Voltage Level (SDI+, SDI-,
SLBI+, SLBI-) ...............................(V
CC
- 0.5V) to (V
CC
+ 0.5V)
Input Current Level (SDI+, SDI-, SLBI+, SLBI-)................±10mA
Voltage at
LOL,
SIS, PHADJ+, PHADJ-,
FIL+, FIL- .................................................-0.5V to (V
CC
+ 0.5V)
PECL Output Current ..........................................................50mA
Continuous Power Dissipation (T
A
= +85°C)
64-Pin TQFP (derate 33.3mW/°C above +85°C)............1.44W
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, PECL loads = 50Ω to (V
CC
- 2V), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC
= +3.3V, T
A
= +25°C.)
PARAMETER
Supply Current
Differential Input Voltage
Single-Ended Input Voltage
Input Termination to V
CC
PECL OUTPUTS (PD_, PCLK±)
T
A
= 0°C to +85°C
PECL Output High Voltage
V
OH
T
A
= -40°C to 0°C
T
A
= 0°C to +85°C
PECL Output Low Voltage
V
OL
T
A
= -40°C to 0°C
TTL INPUTS AND OUTPUTS (SIS,
LOL)
Input High Voltage
Input Low Voltage
Input Current
Output High Voltage
Output Low Voltage
V
OH
V
OL
I
OH
≤
40µA
I
OL
≤
1mA
V
IH
V
IL
-10
2.4
2.0
0.8
+10
V
CC
0.4
V
V
µA
V
V
V
CC
-
1.025
V
CC
-
1.085
V
CC
-
1.81
V
CC
-
1.83
V
CC
-
0.88
V
CC
-
0.88
V
CC
-
1.62
V
CC
-
1.555
SYMBOL
I
CC
V
ID
V
IS
R
IN
Figure 2
CONDITIONS
Excluding PECL outputs
Figure 1
50
V
CC
- 0.4
50
MIN
TYP
160
MAX
240
800
V
CC
+ 0.2
UNITS
mA
mVp-p
V
Ω
SERIAL DATA INPUTS (SDI±, SLBI±)
V
V
2
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, PECL loads = 50Ω to (V
CC
- 2V), T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at
V
CC
= +3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
Serial Data Rate
Parallel Output Data Rate
Parallel Clock-to-Data Output
Delay
t
CLK-Q
Figure 2
f = 70kHz (Note 2)
Jitter Tolerance
f = 100kHz
f = 1MHz
f = 10MHz
Tolerated Consecutive Identical
Digits
Input Return Loss (SDI±, SLBI±)
Output Edge Speed
100kHz to 2.5GHz
2.5GHz to 4.0GHz
200
2.31
1.74
0.38
0.28
SYMBOL
SDI
CONDITIONS
MIN
TYP
2.488
155.52
450
3.3
2.41
0.57
0.46
>2,000
-18
-11
800
Bits
dB
ps
UIp-p
900
MAX
UNITS
Gbps
Mbps
ps
MAX3881
t
R
, t
F
20% to 80%
Note 1:
AC characteristics are guaranteed by design and characterization.
Note 2:
At jitter frequencies <70kHz, the jitter tolerance of the MAX3881 outperforms the ITU/Bellcore specifications.
SDI+
SDI-
25mV MIN
400mV MAX
PCLK
t
CLK-Q
(SDI+) - (SDI-)
V
ID
50mVp-p MIN
800mVp-p MAX
PD0–PD15
Figure 1. Input Amplitude
Figure 2. Timing Parameters
_______________________________________________________________________________________
3
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
MAX3881
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
RECOVERED DATA AND CLOCK
MAX3881-01
SUPPLY CURRENT vs. TEMPERATURE
MAX3881-02
JITTER TOLERANCE
C
F
= 0.1µF
INPUT JITTER (UIp-p)
C
F
= 1.0µF
MAX3881 toc03
200
190
SUPPLY CURRENT (mA)
180
170
160
V
CC
= +3.0V
150
140
10.0
DATA
2
23
- 1 PATTERN
1.0
V
CC
= +3.6V
CLOCK
0.1
-50
-25
0
25
50
75
100
10
TEMPERATURE (°C)
1,000
100
JITTER FREQUENCY (kHz)
10,000
1.64ns/div
JITTER TOLERANCE vs. INPUT VOLTAGE
0.9
MAX3881 toc04
BIT ERROR RATIO vs. INPUT VOLTAGE
MAX3881-05
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
MAX3881-06
1
JITTER FREQUENCY = 1MHz
10
-3
10
-4
BIT ERROR RATIO
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
700
JITTER TOLERNCE (UIp-p)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
600
JITTER FREQUENCY = 5MHz
500
400
SONET SPEC
300
200
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
100
INPUT VOLTAGE (mVp-p)
1000
8.0
8.5
9.0
9.5
10
INPUT VOLTAGE (mVp-p)
4
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
Pin Description
PIN
1, 15, 16, 17,
25, 33, 41,
49, 57, 62,
64
2
3
4, 7, 10, 13,
20, 22, 24,
26, 28, 30,
32, 34, 36,
38, 40, 42,
44, 46, 48,
50, 52, 54,
56, 58, 60
5
6
8
9
11
12
14
18
19
21, 23, 27,
29, 31, 35,
37, 39, 43,
45, 47, 51,
53, 55, 59, 61
63
EP
NAME
FUNCTION
MAX3881
GND
Ground
FIL+
FIL-
Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-.
V
CC
+3.3V Supply Voltage
PHADJ+
PHADJ-
SDI+
SDI-
SLBI+
SLBI-
SIS
PCLK+
PCLK-
Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not
used.
Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to V
CC
if not
used.
Positive Serial Data Input. 2.488Gbps data stream.
Negative Serial Data Input. 2.488Gbps data stream.
Positive System Loopback Input. 2.488Gbps data stream.
Negative System Loopback Input. 2.488Gbps data stream.
Signal Input Selection. TTL low for normal data input (SDI). TTL high for system loopback input
(SLBI).
Positive Parallel Clock PECL Output
Negative Parallel Clock PECL Output
PD0 to PD15
Parallel Data Single-Ended PECL Outputs. Data is updated on the negative transition of the PCLK
signal (Figure 2).
LOL
Exposed Pad
Loss-of-Lock Output. PLL loss-of-lock monitor, TTL active low (internal 10kΩ pullup resistor).
The
LOL
monitor is valid only when a data stream is present on the inputs to the MAX3881.
Ground. This must be soldered to a circuit board for proper electrical and thermal performance
(see
Package Information).
_______________________________________________________________________________________
5
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