The PLL602-89D is a high performance multiple output XO IC chip. It provides 2 pairs of LVDS outputs. The chip
combines a crystal oscillator (XO) with a multiple-output buffer. It accepts a low cost fundamental parallel resonant
mode crystal from 12MHz to 27MHz, which is reproduced at the outputs. The very low jitter (2.5 ps RMS period
jitter) makes this chip ideal for data and telecommunication applications.
BLOCK DIAGRAM
LVDS1_CLK
XIN
XOUT
LVDS1BAR_CLK
Oscillator
Amplifier
LVDS2_CLK
LVDS2BAR_CLK
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04
Page 1
PLL602-89D
12-27 MHz XO IC with 2 Pairs of LVDS Outputs
PIN DESCRIPTION
Name
VDD
XIN
XOUT
GND
LVDSBAR_CLK
LVDS_CLK
Pin
Number
1
2
3
4
5,7
6,8
Type
P
I
I
P
O
O
Description
Power supply.
Crystal input. This is the input of the crystal oscillator circuitry. The crystal
should be mounted as close to the IC as possible, with minimum parasitic
capacitance.
Crystal output. This is the output of the crystal oscillator circuitry. The crystal
should be mounted as close to the IC as possible, with minimum parasitic
capacitance.
Ground.
LVDS complementary output.
LVDS output.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Recommended ESR
SYMBOL
F
XIN
C
L (xtal)
R
E
CONDITIONS
Parallel Fundamental Mode
MIN.
12
TYP.
21.5
MAX.
27
30
UNITS
MHz
pF
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04
Page 2
PLL602-89D
12-27 MHz XO IC with 2 Pairs of LVDS Outputs
3. General Electrical Specifications
PARAMETERS
Supply Current, Dy-
namic (with Loaded
Outputs)
Operating Voltage
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
LVDS outputs
loaded with 100Ω
Fout = 12 MHz
Fout = 25 MHz
MIN.
TYP.
15
20
MAX.
20
25
3.63
UNITS
mA
V
mA
2.25
±50
4. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
2.0V ~ 0.8V with 10 pF load
3.0V ~ 0.3V with 15pF load
Measured @ 1.25 V (LVDS)
Measured @ VDD/2
(CMOS)
SYMBOL
CONDITIONS
MIN.
12
TYP.
MAX.
27
1.5
5
1.5
5
55
55
UNITS
MHz
2
2
50
50
ns
45
45
%
5. Jitter Specifications
PARAMETERS
Period jitter RMS
Peak to Peak jitter
CONDITIONS
With capacitive decoupling between
VDD and GND.
With capacitive decoupling between
VDD and GND. Over 10,000 cycles.
FREQUENCY
25MHz
25MHz
MIN.
TYP.
2.5
18
MAX.
4
30
UNITS
ps
ps
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04
Page 3
PLL602-89D
12-27 MHz XO IC with 2 Pairs of LVDS Outputs
6. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
1.1
1.2
3
±1
-5.7
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
V
out
= V
DD
or GND
V
DD
= 0V
7. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/03/04
Page 4
PLL602-89D
12-27 MHz XO IC with 2 Pairs of LVDS Outputs
PACKAGE INFORMATION
8 PIN SOIC (mm )
Narrow SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
1.27 BSC
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
A
1
e
B
A
C
L
D
E
H
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL602-89D
PART NUMBER
SC
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
PACKAGE TYPE
S=SOIC
Order Number
PLL602-89DSC-R
PLL602-89DSC
Marking
P602-89D SC
P602-89D SC
Package Option
SOIC - Tape and Reel
SOIC - Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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