Preliminary
PLL600-27T/-37T
Low Power 3 Outputs XO 10MHz to 52MHz
FEATURES
•
•
3 CMOS outputs with OE tri-state control
Low current consumption:
PLL600-27T: <4.5mA @ 27MHz with standard
CMOS buffer (3.3V)
PLL600-37T: <3.0mA @ 27MHz with CMOS
compatible Clipped buffer, offering
the lowest current consumption
(3.3V)
10 to 52MHz fundamental crystal input.
Low phase noise (-130 dBc @ 10kHz offset).
Low jitter (RMS): 2.5ps period jitter.
12mA drive capability at TTL output.
1.62V to 3.63V DC operation.
Available in 8 pin SOIC.
PIN ASSIGNMENT
XIN/FIN
OE^
CLK1
GND
1
PLL600-X7T
2
3
4
8
7
6
5
XOUT
CLK0
VDD
CLK2
•
•
•
•
•
•
^: Denotes internal Pull-up
DESCRIPTION
The PLL600-27T/-37T form a low cost family of XO
IC’s, designed to replace multiple XO solutions sav-
ing the cost and board space of clock distribution
buffers. In addition, they provide among the lowest
current on the market for the 10MHz to 52MHz
range. They accept input crystals from 10 to 52MHz
(fundamental resonant mode) and provide low phase
noise (<-130dBc at 10kHz offset at 30MHz), and very
low jitter (2.5 ps RMS period jitter) outputs.
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
OSC
CLK0
CLK1
CLK2
OE
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 1
Preliminary
PLL600-27T/-37T
Low Power 3 Outputs XO 10MHz to 52MHz
PIN DESCRIPTION
Name
XIN/FIN
OE
CLK1
GND
CLK2
VDD
CLK0
XOUT
Pin #
1
2
3
4
5
6
7
8
Type
I
I
O
P
O
P
O
I
Description
Crystal input ( 10MHz to 52MHz ) or Ref Clock input.
Output Enable input. This pin has internal pull-up resistor. All outputs will be
tri-stated when low.
Output clock.
Ground.
Output clock.
Power supply.
Output clock.
Crystal output.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Electrical Specifications
PARAMETERS
Input Crystal Frequency
Settling time
Output Clock Rise/Fall Time
VDD sensitivity
Output Clock Duty Cycle
Short Circuit Current
At power-up
(Vdd reaches 1.62V)
0.8V ~ 2.0V with 10 pF load
0.3V ~ 3.0V with 15 pF load
Frequency vs. VDD +/- 10%
Measured @ 50% V
DD
CONDITIONS
MIN.
10
TYP.
MAX.
52
10
UNITS
MHz
ms
ns
1.15
2.4
0.8
45
50
±50
0.8
55
ppm
%
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 2
Preliminary
PLL600-27T/-37T
TYP.
2.1
-80
-110
-130
-138
-145
Low Power 3 Outputs XO 10MHz to 52MHz
3. Jitter and Phase Noise Specifications
PARAMETERS
RMS Period Jitter
(1 sigma – 1000 samples)
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling
between VDD and GND.
30MHz @100Hz offset
30MHz @1kHz offset
30MHz @10kHz offset
30MHz @100kHz offset
30MHz @1MHz offset
MIN.
MAX.
2.5
UNITS
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
4. DC Specifications
PARAMETERS
Supply Current, Dynamic,
with Loaded Outputs
(at VDD = 3.3V)
Respectively for PLL600
-27T/-37T
Supply Current in tri-state
Operating Voltage
Output High Voltage
Output Low Voltage
Output High Voltage at
CMOS level (PLL600-27T)
Output drive current
(PLL600-27T)
(1):
SYMBOL
CONDITIONS
At 10MHz, Cload=15pF
At 13.5MHz, Cload=15pF
At 17.7MHz, Cload=15pF
At 27MHz, Cload=15pF
At 48MHz, Cload=15pF
Output disabled
-27T I
OH
= -12mA
(1)
(3.3V)
-37T
(1)
, I
OH
= -12mA
(1)
(3.3V)
-27T I
OL
= 12mA
(1)
(3.3V)
-37T
(1)
, I
OL
= 12mA
(1)
(3.3V)
I
OH
= -4mA
At TTL level (3.3V)
MIN.
TYP.
2.0
2.4
3.0
4.0
7.0
/
/
/
/
/
1.5
1.6
2.0
2.5
4.0
MAX.
2.5 / 2.0
3.0 / 2.0
3.5 / 2.5
4.5 / 3.0
7.5 / 4.5
520
3.63
UNITS
I
DD
mA
I
DD
V
DD
V
OH
V
OL
V
OHC
1.62
2.4
2.4
2.9
0.32
0.4
0.4
µA
V
V
V
V
V
V
V
DD
– 0.4
12
17
mA
P600-37T has non-standard CMOS VOH and VOL levels for lower current consumption, but meets CMOS input stage needs. P600-37T
should be used to drive pure capacitive loads only.
5. Crystal Specifications
PARAMETERS
Crystal Resonator Frequency
Crystal Loading Rating
Maximum Sustainable Drive Level
Operating Drive Level
C0 (for frequencies below 30MHz)
C0 (for frequencies above 30MHz)
ESR
SYMBOL
F
XIN
C
L (xtal)
MIN.
10
TYP.
8.5
MAX.
52
200
UNITS
MHz
pF
µW
µW
pF
pF
Ω
50
5
4
30
R
S
Note:
A detailed crystal specification document is also available for this part
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 3
Preliminary
PLL600-27T/-37T
Low Power 3 Outputs XO 10MHz to 52MHz
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC
Symbol
A
A1
B
C
D
E
H
L
e
Min.
1.47
0.10
0.33
0.19
4.80
3.80
5.80
0.38
Max.
1.73
0.25
0.51
0.25
4.95
4.00
6.20
1.27
1.27 BSC
A
1
e
B
A
C
L
D
E
H
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL600-X7T
PART NUMBER
SC
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
PACKAGE TYPE
S=SOIC
Order Number
PLL600-27T SC
PLL600-27T SC-R
PLL600-37T SC
PLL600-37T SC-R
Marking
P600-27T
P600-27T
P600-37T
P600-37T
SC
SC
SC
SC
Package Option
8 pin SOIC - Tubes
8 pin SOIC - Tape and Reel
8 pin SOIC - Tubes
8 pin SOIC - Tape and Reel
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur-
nished by PhaseLink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the ex-
press written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 08/12/04 Page 4
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
