PLL520-40
CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
FEATURES
•
•
•
•
•
•
•
•
65MHz to 130MHz Fundamental Mode Crystal.
Output range: 65MHz – 130MHz (no PLL).
Low Injection Power for crystal 50uW.
CMOS outputs (High Drive (30mA) or Standard
Drive (10mA) output).
Integrated variable capacitors.
Supports 2.5V or 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
62 mil
DIE CONFIGURATION
65 mil
DRIVE_SEL^
Reserved
VDD
VDD
VDD
VDD
N/C
N/C
(1550,1475)
17
16
25
24
23
22
21
20
19
18
GNDBUF
CMOS
N/C
N/C
VDDBUF
VDDBUF
CMOS
N/C
N/C
XIN
XOUT
N/C
N/C
OE
CTRL^
VCON
26
27
Die ID:
A1313-13C
15
28
14
DESCRIPTION
The PLL520-40 is a VCXO IC specifically designed
to pull frequency fundamental crystals from 65MHz
to 130MHz, with CMOS outputs. Its design was
optimized to tolerate higher limits of interelectrode
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
13
29
12
11
30
C502A
31
1
2
3
4
5
6
7
8
10
9
GND
Reserved
Y
(0,0)
X
Note: ^ denotes internal pull up
DIE SPECIFICATIONS
Name
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
BLOCK DIAGRAM
OE
VCON
Oscillator
XIN
XOUT
Amplifier
w/
integrated
varicaps
Size
Reverse side
Pad dimensions
Thickness
DRIVE_SEL AND OE_CTRL TABLE
Q
DRIVE_SEL
(Pad #19)
0
1
OE_CTRL
(Pad #30)
0
1
Output Drive
High Drive CMOS
Standard CMOS (default)
State
Tri-state
Output enabled (default)
PLL520-40
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1
GNDBUF
GNDBUF
GND
GND
GND
GND
PLL520-40
CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications
PARAMETERS
Built-in Capacitance
Inter-electrode capacitance
C0/C1 ratio (gamma)
Oscillation Frequency
SYMBOL
CX+
CX-
C
0
γ
OF
CONDITIONS
65MHz to 130MHz
(VDD=3.3V)
MIN.
TYP.
MAX.
2
2
UNITS
pF
-
MHz
2.6
65
300
130
Fund.
3. Voltage Control Crystal Oscillator
PARAMETERS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
On-chip Varicaps control range
Linearity
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
SYMBOL
T
VCXOSTB
CONDITIONS
From power valid
F
XIN
= 100 – 200MHz;
XTAL C
0
/C
1
< 250
0V
≤
VCON
≤
3.3V
VCON=1.65V,
±1.65V
VCON = 0 to 3.3V
MIN.
TYP.
MAX.
10
UNITS
ms
ppm
ppm
pF
%
ppm/V
kΩ
kHz
200*
±100*
4 – 18*
10*
65
60
0V
≤
VCON
≤
3.3V, -3dB
25
Note:
Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 2
PLL520-40
CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
4. General Electrical Specifications
PARAMETERS
Supply Current (Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
I
DD
V
DD
CONDITIONS
MIN.
2.97
45
TYP.
MAX.
40
3.63
55
UNITS
mA
V
%
mA
@ 50% V
DD
(CMOS)
50
±50
5. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Integrated jitter RMS
CONDITIONS
77.76MHz
77.76MHz
Integrated 12 kHz to 20 MHz at
77.76MHz
MIN.
TYP.
2.5
18.5
0.5
MAX.
UNITS
ps
ps
ps
6. Phase Noise Specifications
PARAMETERS
Phase Noise relative
to carrier
Note: Phase Noise at VCON = 0V
FREQUENCY
77.76MHz
@10Hz
-75
@100Hz
-95
@1kHz
-125
@10kHz
-145
@100kHz
-155
UNITS
dBc/Hz
7. CMOS Output Electrical Specifications
PARAMETERS
Output drive current
(High Drive)
Output drive current
(Standard Drive)
Output Clock Rise/Fall Time
(Standard Drive)
Output Clock Rise/Fall Time
(High Drive)
SYMBOL
I
OH
I
OL
I
OH
I
OL
CONDITIONS
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
V
OH
= V
DD
-0.4V, V
DD
=3.3V
V
OL
= 0.4V, V
DD
= 3.3V
0.3V ~ 3.0V with 15 pF load
0.3V ~ 3.0V with 15 pF load
MIN.
30
30
10
10
TYP.
MAX.
UNITS
mA
mA
mA
mA
2.4
1.2
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 3
PLL520-40
CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
PAD ASSIGNMENT
Pad #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
Optional GND
Optional GND
Optional GND
Optional GND
GND
Reserved
Optional GNDBUF
Optional GNDBUF
Not connected
Not connected
CMOS OUT
VDDBUF
Optional VDDBUF
Not connected
Not connected
Optional CMOS OUT
GNDBUF
Reserved
DRIVE_SEL
Not connected
Optional VDD
Optional VDD
VDD
Optional VDD
Not connected
XIN
XOUT
Not connected
Not connected
OE_CTRL
VCON
X (µm)
248
361
473
587
702
874
1042
1171
1400
1400
1400
1400
1400
1400
1400
1400
1389
1232
1042
854
659
559
459
358
194
109
109
109
109
109
109
Y (µm)
109
109
109
109
109
109
109
109
125
259
476
616
716
871
1089
1227
1365
1365
1365
1365
1365
1365
1365
1365
1365
1223
1017
858
646
397
181
Optional Ground.
Optional Ground.
Optional Ground.
Optional Ground.
Ground.
Reserved for future use.
Optional Ground, buffer circuitry.
Optional Ground, buffer circuitry.
Not Connected.
Not Connected..
CMOS output.
Power supply, buffer circuitry.
Optional power supply, buffer circuitry.
Not Connected.
Not Connected.
Optional CMOS output.
Ground, buffer circuitry.
Reserved for future use.
Used to select drive strength. See DRIVE_SEL AND
OE_CTRL TABLE on page 1.
Not Connected.
Optional power supply.
Optional power supply.
Power supply.
Optional power supply.
Not Connected.
Crystal input. See Crystal Specifications on page 2.
Crystal output. See Crystal Specifications on page 2.
Not Connected.
Not Connected.
Used to enable/disable the output(s). See
DRIVE_SEL AND OE_CTRL TABLE on page 1.
Internal pull up.
Voltage control input.
Description
Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 4
PLL520-40
CMOS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PLL520-40 D C
PART NUMBER
TEMPERATURE
C=COMMERCIAL
I=INDUSTRAL
PACKAGE TYPE
D=DIE
Order Number
PLL520-40DC
Marking
P520-40DC
Package Option
Die – Waffle Pack
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY:
PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 5
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