performance clock synthesizer. With PhaseLink proprietary
analog Phase Locked Loop techniques, the chip accepts
25.0 MHz crystal, and produces multiple output clocks for
networking chips. A CLKOUT signal of selectable
frequency (25MHz, 48MHz, 50MHz, 90MHz, 100MHz,
125MHz, 133MHz, 145MHz or 150 MHz) is available at 5
output pins. Through an SST enable (SSTE) selector, the
CLKOUT signal can be modulated to reduce EMI through
Spread Spectrum Technology. Output enable selectors are
available to enable/disable the output signals.
SELECTION TABLE
FS1
0
0
0
1
1
1
FS0
0
M
1
0
M
1
CLKOUT
90 MHz
100 MHz
125 MHz
133 MHz
145 MHz
150 MHz
SSTE
0
1
SST
MODULATION
±0.25%
Center
OFF
Tri-level input pins: 0 = connect to GND
M= not connected, 1 = connect to VDD
BLOCK DIAGRAM
25M_EN (enable)
XIN
XOUT
XTAL
OSC
1
25MHz
50M_EN (enable)
FS (0:1)
Control
Logic
1
50MHz
CLKOUT_EN (enable)
SSTE
(SST enable)
5
CLKOUT (90 100, 125, 133,
145 or 150 MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 05/31/05 Page 1
P r e lim ina ry
PLL650-04
Low EMI Clock for 10/100 PHY and Gigabit Ethernet
PIN DESCRIPTIONS
Name
XIN
XOUT/SSTE
GND
VDD
CLKOUT_EN
CLKOUT
FS0
FS1
50 MHz
Number
1
2
3,11,15,17
4,6,20
5
7,8,10,12,14
13
9
16
Type
I
B
P
P
I
O
TL
I
O
Description
Crystal input to be connected to a 25MHz fundamental parallel mode
crystal (C
L
=20pF).
Crystal connector. At power-up, the SSTE value that enables/disables the
spread spectrum function is latched in. 120kΩ internal pull up resistor.
Ground.
3.3V power supply.
CLKOUT enable pin. Disables CLKOUT to tri-state if ‘low’ (logical 0).
Internal 60kΩ pull-up resistor defaults it to ‘high’ (logical 1).
CLKOUT outputs with selectable frequency through FS(0:1). CLKOUT can
be modulated using SST to reduce EMI through SSTE. CLKOUT can be
disabled to tri-state with CLKOUT_EN.
Tri-level frequency selector pin (See selection table on p.1). 0: connected
to GND, 1: connected to VDD, M: not connected.
Frequency selector pin (standard bi-level ‘1’ or ‘0’). See table on p.1.
Internal 60kΩ pull-up resistor defaults it to ‘high’ (logical 1).
50 MHz output. This output is not modulated with Spread Spectrum. This
output can be disabled to tri-state with 50M_EN.
25 MHz output, not modulated with Spread Spectrum. Bi-directional pin: at
power-up, the input value 25M_EN is latched-in. If 25M_EN (25MHz output
enable) is low, the pin will be disabled to tri-state after power-up, if
25M_EN is high, the out pin will be enabled and provide a 25 MHz output
signal after power-up. Internal 60kΩ pull-up resistor defaults it to ‘high’
(logical 1).
50 MHz output enable pin. Disables the 50MHz output to tri-state if ‘low’
(logical 0). Internal 60kΩ pull-up resistor defaults it to ‘high’ (logical 1).
25 MHz/25M_EN
18
B
50M_EN
19
I
FUNCTIONAL DESCRIPTION
Selectable spread spectrum and output frequencies
The PLL650-04 provides selectable spread spectrum modulation and selectable output frequencies for the CLKOUT signal.
Selection is made by connecting specific pins to a logical “zero” or “one”, according to the frequency and spread spectrum
selection tables shown on page 1.
In order to reduce the number of pins on the chip, the PLL650-04 uses bi-directional pins that serve as inputs upon power-up,
and as outputs as soon as the inputs have been latched.
Pins 2 (SSTE) is a bi-directional pin used as input to enable/disable the spread spectrum modulation upon power-up, and used
as XOUT crystal connection after the SSTE input signal has been latched. Pin 18 (25M_EN) is a bi-directional pin used to
enable/disable the 25MHz output upon power-up. After the input signal has been latched, pin 18 will serve as 25 MHz output or
will be disabled, depending on the power-up value of 25M_EN.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 05/31/05 Page 2
P r e lim ina ry
PLL650-04
Low EMI Clock for 10/100 PHY and Gigabit Ethernet
Connecting a selection pin to a logical “one”
The output enable and spread spectrum selection pins have an internal pull-up resistor (60kΩ for all selection pins except for
pin 2 (SSTE), which has a 120kΩ internal pull-up). This internal pull-up resistor will pull the input value to a logical “one” (pull-
up) by default, i.e. when no resistive load is connected between the pin and GND. No external pull-up resistor is therefore
required for connecting a logical “one” upon power-up.
Note:
when the output load presents a low impedance in comparison to
the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up to a logical “one”, and an
external pull-up resistor may be required.
Connecting a selection pin to a logical “zero”
Connecting the bi-directional pin to a logical “zero” does require the use of an external loading resistor between the pin and
GND that has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V
(logical “zero”). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor
should however be kept as large as possible. In general, it is recommended to use an external resistor of around one sixth to
one quarter of the internal pull-up resistor (see Application Diagram).
Note:
when the output is used to drive a load presenting
an small resistance between the output pin and VDD, this resistance is in essence connected in parallel to the internal pull-up
resistor. In such a case, the external pull-down resistor may have to be dimensioned smaller to guarantee that the pin voltage
will be low enough achieve the desired logical “zero”. This is particularly true when driving 74FXX TTL components.
Selecting the output frequency (CLKOUT) with the tri-level selection pin
The CLKOUT frequency is selected with the tri-level FS(0:1) input pins, as per the frequency selection table on page 1. Unlike
the other bi-level selection pins, the tri-level input pins are in the “M” (mid) state when not connected. In order to connect a tri-
level pin to a logical “zero”, the pin must be connected to GND. Similarly, in order to connect a tri-level pin to a logical “one”, the
pin must be connected to VDD. No external pull-up or pull-down resistor is required with the tri-level selector pins.
APPLICATION DIAGRAM
Internal to chip
VDD
External Circuitry
R
up
Power Up
Reset
R
RB
Output
EN
Bi-directional pin
Clock Load
Latched
Input
Latch
R
UP
/
4
Jumper options
NOTE:
Rup=120kΩ for SSTE (Pin2); Rup=60k
Ω
for 25M_EN (Pin18). R starts from 1 to 0 while RB starts from 0 to 1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 05/31/05 Page 3
P r e lim ina ry
PLL650-04
Low EMI Clock for 10/100 PHY and Gigabit Ethernet
Electrical Specifications
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
MIN.
-0.5
-0.5
-65
-40
MAX.
4.6
V
DD
+0.5
V
DD
+0.5
150
85
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied.
*
Note:
Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. AC Specifications
PARAMETERS
Input Frequency
Output Rise Time
Output Fall Time
Duty Cycle
Max. Absolute Jitter
Max. Jitter, cycle to cycle
Output to output skew
PLL Lock Time
Measured at V
DD
/2 on the
CLKOUT pin
After V
DD
>90% V
DD
-END
Value
0
3
0.8V to 2.0V with no load
2.0V to 0.8V with no load
At VDD/2
Short term
45
50
±150
80
250
5
CONDITIONS
MIN.
10
TYP.
24
MAX.
27
1.5
1.5
60
UNITS
MHz
ns
ns
%
ps
ps
ps
ms
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 05/31/05 Page 4
P r e lim ina ry
PLL650-04
Low EMI Clock for 10/100 PHY and Gigabit Ethernet
3. DC Specifications
PARAMETERS
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage At
CMOS Level
Operating Supply Current
Short-circuit Current
Internal pull-up resistor
Internal pull-up resistor
SYMBOL
V
DD
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
I
DD
I
S
R
up
R
up
CONDITIONS
MIN.
2.97
TYP.
V
DD
/2
V
DD
/2
MAX.
3.63
V
DD
/2 - 1
0.5
UNITS
V
V
V
V
V
V
V
V
V
V
For all Tri-level input
For all Tri-level input
For all normal input
For all normal input
I
OH
= -25mA
I
OL
= 25mA
I
OH
= -8mA
No Load
V
DD
-0.5
2
0.8
2.4
0.4
V
DD
-0.4
35
±100
mA
mA
kΩ
kΩ
Pins 5,18,19
Pin 2
60
120
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
