Preliminary
PLL602-10
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
FEATURES
•
•
•
•
•
•
Low phase noise output for the 96MHz to
400MHz range (-134 dBc at 10kHz offset).
Selectable CMOS, PECL and LVDS output.
12 to 25MHz crystal input.
Output Enable selector.
3.3V operation.
Available in DIE (65 mil x 62 mil).
DIE CONFIGURATION
65 mil
(1550,1475)
19
18
17
16
25
26
24
23
22
21
20
27
15
28
14
62 mil
13
29
12
11
30
DESCRIPTIONS
31
10
9
1
2
3
4
5
6
7
8
The PLL602-10 is a monolithic low jitter and low
phase noise (-134dBc/Hz @ 10kHz offset) XO IC
Die, with CMOS, LVDS and PECL output, for 96MHz
to 400MHz output range, using a low frequency
crystal.
The same die can be used as a XO with output
frequencies ranging from F
XIN
x 8 to F
XIN
x 16 thanks
to selector pads allowing bonding options (see
Divider Selection Table on this page). This makes
the PLL602-10 ideal for a wide range of applications.
Y
X
(0,0)
MULTIPLIER SELECTION
Pad #19
MULTIPLIER
OUTPUT RANGE
0
1
F
XIN
x 16
F
XIN
x 8
192 – 400 MHz
96 – 200 MHz
Note:
Selector pad defaults to ‘1’, wire bond to GND to set to ‘0’
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
62 x 65 mil
GND
80 micron x 80 micron
10 mil
OUTPUT SELECTION AND ENABLE
Pad #18
OUTSEL1
0
0
1
1
Pad #25
OUTSEL0
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
PECL
LVDS
State
Tri-state
Output enabled
OE (Pad #30)
0
1 (Default)
BLOCK DIAGRAM
VCO
Divider
SELECT
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLKBAR
CLK
XIN
XOUT
XTAL
OSC
OE
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 1
Preliminary
PLL602-10
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
Junction Temperature
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
SYMBOL
V
DD
V
I
V
O
T
S
T
A
T
J
V
SS
-
0.5
V
SS
-
0.5
-65
0
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
150
70
125
260
2
UNITS
V
V
V
°C
°C
°C
°C
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. Crystal Specifications
PARAMETERS
Crystal Resonator
Frequency
Crystal Loading Rating
Recommended ESR
SYMBOL
F
XIN
C
L
(xtal)
R
E
AT cut
CONDITIONS
Parallel Fundamental
Mode
MIN.
12
TBD
30
TYP.
MAX.
25
UNITS
MHz
pF
Ω
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 2
Preliminary
PLL602-10
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
3. General Electrical Specifications
PARAMETERS
Supply Current, Dynamic
(with Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
4. Jitter and Phase Noise specification
PARAMETERS
Period jitter RMS
Accumulated jitter RMS
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
CONDITIONS
With capacitive decoupling
between VDD and GND.
With capacitive decoupling
between VDD and GND. Over
10,000 cycles.
155MHz @100Hz offset
155MHz @1kHz offset
155MHz @10kHz offset
155MHz @100kHz offset
MIN.
TYP.
7
11
-90
-114
-134
-134
MAX.
UNITS
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
SYMBOL
I
DD
V
DD
@ 1.4V (CMOS)
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
CONDITIONS
PECL/LVDS/CMOS
3.13
45
45
45
MIN.
TYP.
MAX.
80/60/35
3.47
55
55
55
UNITS
mA
V
%
mA
50
50
50
±50
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 3
Preliminary
PLL602-10
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
5. LVDS Electrical Characteristics
PARAMETERS
Output Differential Voltage
V
DD
Magnitude Change
Output High Voltage
Output Low Voltage
Offset Voltage
Offset Magnitude Change
Power-off Leakage
Output Short Circuit Current
6. LVDS Switching Characteristics
PARAMETERS
Differential Clock Rise Time
Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
V
OD
∆V
OD
V
OH
V
OL
V
OS
∆V
OS
I
OXD
I
OSD
CONDITIONS
MIN.
247
-50
TYP.
355
1.4
MAX.
454
50
1.6
1.375
25
±10
-8
UNITS
mV
mV
V
V
V
mV
uA
mA
R
L
= 100
Ω
(see figure)
0.9
1.125
0
1.1
1.2
3
±1
-5.7
V
out
= V
DD
or GND
V
DD
= 0V
SYMBOL
t
r
t
f
CONDITIONS
R
L
= 100
Ω
C
L
= 10 pF
(see figure)
MIN.
0.2
0.2
TYP.
0.7
0.7
MAX.
1.0
1.0
UNITS
ns
ns
LVDS Switching Test Circuit
OUT
50Ω
C
L
= 10pF
V
OD
V
OS
V
DIFF
R
L
= 100Ω
50Ω
C
L
= 10pF
OUT
OUT
LVDS Transistion Time Waveform
OUT
0V (Differential)
OUT
80%
V
DIFF
20%
0V
80%
20%
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 4
Preliminary
PLL602-10
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
7. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
V
OH
V
OL
CONDITIONS
R
L
= 50
Ω
to (V
DD
– 2V)
(see figure)
MIN.
V
DD
– 1.025
V
DD
– 1.620
MAX.
UNITS
V
V
8. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
t
r
t
f
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
TYP.
0.6
0.5
MAX.
1.5
1.5
UNITS
ns
ns
PECL Levels Test Circuit
OUT
VDD
OUT
PECL Output Skew
50Ω
2.0V
50%
50Ω
OUT
OUT
t
SKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT
80%
50%
20%
OUT
t
R
t
F
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 5
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