Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
FEATURES
•
’Trench’
technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
• Logic level compatible
PHP55N04LT, PHB55N04LT
PHD55N04LT
QUICK REFERENCE DATA
d
SYMBOL
V
DSS
= 35 V
I
D
= 55 A
R
DS(ON)
≤
14 mΩ (V
GS
= 10 V)
R
DS(ON)
≤
18 mΩ (V
GS
= 5 V)
g
s
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP55N04LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB55N04LT is supplied in the SOT404 (D
2
PAK) surface mounting package.
The PHD55N04LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
PIN
1
2
3
tab
DESCRIPTION
gate
drain
1
source
SOT78 (TO220AB)
tab
SOT404 (D
2
PAK)
tab
SOT428 (DPAK)
tab
2
1 23
2
1
3
1
3
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
DM
P
tot
T
j
, T
stg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
CONDITIONS
T
j
= 25 ˚C to 175˚C
T
j
= 25 ˚C to 175˚C; R
GS
= 20 kΩ
T
j
≤
150˚C
T
mb
= 25 ˚C
T
mb
= 100 ˚C
T
mb
= 25 ˚C
T
mb
= 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
35
35
±
15
±
20
55
38
220
103
175
UNIT
V
V
V
V
A
A
A
W
˚C
1
It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
January 2001
1
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
R
th j-a
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
PHP55N04LT, PHB55N04LT
PHD55N04LT
MIN.
-
TYP. MAX. UNIT
-
60
50
1.45
-
-
K/W
K/W
K/W
SOT78 package, in free air
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
-
-
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
CONDITIONS
MIN.
-
MAX.
60
UNIT
mJ
Drain-source non-repetitive I
D
= 25 A; V
DD
≤
15 V;
unclamped inductive turn-off V
GS
= 5 V; R
GS
= 50
Ω;
T
mb
= 25 ˚C
energy
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA;
T
j
= -55˚C
V
DS
= V
GS
; I
D
= 1 mA
T
j
= 175˚C
T
j
= -55˚C
V
GS
= 10 V; I
D
= 25 A
V
GS
= 10 V; I
D
= 25 A (SOT428 package)
V
GS
= 5 V; I
D
= 25 A
V
GS
= 5 V; I
D
= 25 A; T
j
= 175˚C
Forward transconductance
V
DS
= 25 V; I
D
= 25 A
Gate source leakage current V
GS
=
±5
V; V
DS
= 0 V
Zero gate voltage drain
V
DS
= 25 V; V
GS
= 0 V;
current
T
j
= 175˚C
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal drain inductance
Internal source inductance
Input capacitance
Output capacitance
Feedback capacitance
I
D
= 55 A; V
DD
= 15 V; V
GS
= 5 V
MIN.
35
32
1
0.5
-
-
-
-
-
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP. MAX. UNIT
-
-
1.5
-
-
11
14
15
-
28
10
0.05
-
20
8
9
7
56
57
38
3.5
4.5
7.5
1230
354
254
-
-
2
-
2.3
14
16
18
34
-
100
10
500
-
-
-
15
80
80
50
-
-
-
-
-
-
V
V
V
V
V
mΩ
mΩ
mΩ
mΩ
S
nA
µA
µA
nC
nC
nC
ns
ns
ns
ns
nH
nH
nH
pF
pF
pF
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
L
d
L
d
L
s
C
iss
C
oss
C
rss
V
DD
= 15 V; I
D
= 25 A;
V
GS
= 10 V; R
G
= 5
Ω
Resistive load
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 20 V; f = 1 MHz
January 2001
2
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP55N04LT, PHB55N04LT
PHD55N04LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
I
S
I
SM
V
SD
t
rr
Q
rr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
MIN.
-
-
I
F
= 25 A; V
GS
= 0 V
I
F
= 55 A; V
GS
= 0 V
I
F
= 20 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= 25 V
-
-
-
-
TYP. MAX. UNIT
-
-
0.9
1.0
87
0.1
55
220
1.2
-
-
-
A
A
V
ns
µC
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
1000
Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
100
tp = 10 us
100 us
10
1 ms
D.C.
10 ms
100 ms
1
1
10
Drain-Source Voltage, VDS (V)
100
Fig.1. Normalised power dissipation.
PD% = 100⋅P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.3. Safe operating area
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Transient thermal impedance, Zth j-mb (K/W)
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0
25
50
75
100
125
Mounting Base temperature, Tmb (C)
150
175
10
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
D
tp
D = tp/T
single pulse
0.01
1E-06
1E-05
1E-04
1E-03
Pulse width, tp (s)
1E-02
T
1E-01
1E+00
Fig.2. Normalised continuous drain current.
ID% = 100⋅I
D
/I
D 25 ˚C
= f(T
mb
); V
GS
≥
5 V
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
January 2001
3
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP55N04LT, PHB55N04LT
PHD55N04LT
50
45
40
35
30
25
Drain Current, ID (A)
VGS = 10 V
5V
4.5 V
Tj = 25 C
30
Transconductance, gfs (S)
VDS > ID X RDS(ON)
25
Tj = 25 C
20
3V
15
2.8 V
175 C
20
15
10
5
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Drain-Source Voltage, VDS (V)
1.6
1.8
2.6 V
2.4 V
2.2 V
2V
2
0
0
5
10
15
20
25
Drain current, ID (A)
30
35
40
10
5
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
); conditions: V
DS
= 25 V
Normalised On-state Resistance
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
0.09
0.08
3V
0.07
0.06
0.05
0.04
0.03
5V
0.02
0.01
0
0
5
10
15
20
25
30
Drain Current, ID (A)
35
40
45
50
VGS =4.5 V
2.2 V
2.4 V
2.6 V
2.8V
Tj = 25 C
10V
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-60
-40
-20
0
20
40
60
80
100
Junction temperature, Tj (C)
120
140
160
180
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
Fig.9. Normalised drain-source on-state resistance.
a = R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Threshold Voltage, VGS(TO) (V)
2.25
2
1.75
maximum
Drain current, ID (A)
40
VDS > ID X RDS(ON)
35
30
1.5
25
1.25
typical
20
1
minimum
15
0.75
10
175 C
5
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Gate-source voltage, VGS (V)
Tj = 25 C
0.5
0.25
0
-60
-40
-20
0
20
40
60
80
100
120
140
160
180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
) ; conditions: V
DS
= 25 V; parameter T
j
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
January 2001
4
Rev 1.000
Philips Semiconductors
Product specification
N-channel TrenchMOS transistor
Logic level FET
PHP55N04LT, PHB55N04LT
PHD55N04LT
1.0E-01
Drain current, ID (A)
VDS = 5 V
Gate-source voltage, VGS (V)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
2.5
3
ID = 55A
Tj = 25 C
VDD = 15 V
1.0E-02
1.0E-03
minimum
1.0E-04
typical
maximum
1.0E-05
1.0E-06
0
0.5
1
1.5
2
Gate-source voltage, VGS (V)
5
10
15
20
25
30
Gate charge, QG (nC)
35
40
45
50
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
); parameter V
DS
Source-Drain Diode Current, IF (A)
Capacitances, Ciss, Coss, Crss (pF)
10000
50
VGS = 0 V
45
40
35
30
Ciss
1000
25
20
15
Coss
Crss
10
5
0
100
0.1
1
10
Drain-Source Voltage, VDS (V)
100
0
0.1
0.2
0.3 0.4
0.5
0.6
0.7
0.8
0.9
1
1.1 1.2
1.3
1.4
1.5
Source-Drain Voltage, VSDS (V)
Tj = 25 C
175 C
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
January 2001
5
Rev 1.000
嵌入式系统
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