CERAMIC CHIP CAPACITORS
INTRODUCTION
Ceramic chips consist of formulated ceramic
dielectric materials which have been fabricated into thin
layers, interspersed with metal electrodes alternately
exposed on opposite edges of the laminated structure.
The entire structure is then fired at high temperature to
produce a monolithic block which provides high capaci-
tance values in a small physical volume. After firing, con-
ductive terminations are applied to opposite ends of the
chip to make contact with the exposed electrodes.
Standard end terminations use a nickel barrier layer and
a tin overplate to provide excellent solderability for the
customer.
KEMET multilayer ceramic chip capacitors are
produced in plants designed specifically for chip capa-
citor manufacture. The process features a high degree
of mechanization as well as precise controls over raw
materials and process conditions. Manufacturing is
supplemented by extensive Technology, Engineering
and Quality Assurance programs.
KEMET ceramic chip capacitors are offered in the
five most popular temperature characteristics. These
are designated by the Electronics Industies Association
(EIA) as the ultra-stable C0G (also known as NP0,
military version BP), the stable X7R (military BX or
BR), the stable X5R, and the general purpose Z5U and
Y5V. A wide range of sizes are available. KEMET multi-
layer ceramic chip capacitors are available in KEMET's
tape and reel packaging, compatible with automatic
placement equipment. Bulk cassette packaging is also
available (0805,0603 and 0402 only) for those pick and
place machines requiring its use.
Table 1 – EIA Temperature Characteristic
Codes for Class I Dielectrics
Significant Figure
of Temperature
Coefficient
PPM per
Degree C
0.0
0.3
0.9
1.0
1.5
Letter
Symbol
C
B
A
M
P
Multiplier Applied
to Temperature
Coefficient
Multi-
plier
-1
-10
-100
-1000
-10000
Number
Symbol
0
1
2
3
4
Tolerance of
Temperature
Coefficient
PPM per
Degree C
±
30
±
60
±
120
±
250
±
500
Letter
Symbol
G
H
J
K
L
KEMET supplies the C0G characteristic.
For Class II and III dielectrics (including X7R,
X5R, Z5U & Y5V), the first symbol indicates the
lower limit of the operating temperature range, the
second indicates the upper limit of the operating
temperature range, and the third indicates the
maximum capacitance change allowed over the
operating temperature range. EIA type designa-
tion codes for Class II and III dielectrics are
shown in Table 2.
Table 2 – EIA Temperature Characteristic Codes for
Class II & III Dielectrics
Low Temperature
Rating
Degree
Celsius
+10C
-30C
-55C
Letter
Symbol
Z
Y
X
High Temperature
Rating
Degree
Celsius
+45C
+65C
+85C
+105C
+125C
+150C
+200C
Number
Symbol
2
4
5
6
7
8
9
Maximum Capacitance
Shift
Percent
±
1.0%
±
1.5%
±
2.2%
±
3.3%
±
4.7%
±
7.5%
±
10.0%
±
15.0%
±
22.0%
+ 22/-33%
+22/-56%
+22/-82%
Letter
Symbol
A
B
C
D
E
F
P
R
S
T
U
V
EIA
Class
II
II
II
II
II
II
II
II
III
III
III
III
KEMET supplies the X7R, X5R, Z5U and Y5V characteristics.
3.
4.
ELECTRICAL CHARACTERISTICS
1.
Working Voltage:
Refers to the maximum continuous DC working
voltage permissible across the entire operating
temperature range. The reliability of multilayer
ceramic capacitors is not extremely sensitive to
voltage, and brief applications of voltage above
rated will not result in immediate failure. However,
reliability will be degraded by sustained exposure
to voltages above rated.
Temperature Characteristics:
Within the EIA classifications, various tempera-
ture characteristics are identified by a three-symbol
code; for example: C0G, X7R, X5R, Z5U and Y5V.
For Class I temperature compensating
dielectrics (includes C0G), the first symbol desig-
nates the significant figures of the temperature
coefficient in PPM per degree Celsius, the second
designates the multiplier to be applied, and the
third designates the tolerance in PPM per
degrees Celsius. EIA temperature characteristic
codes for Class I dielectrics are shown in Table 1.
Capacitance Tolerance:
See tables on pages
73-76.
Capacitance:
Within specified tolerance when measured per
Table 3.
The standard unit of capacitance is the farad.
For practical capacitors, capacitance is usually
expressed in microfarads (10
-6
farad), nanofarads
(10
-9
farad), or picofarads (10
-12
farad). Standard
measurement conditions are listed in Table 3 -
Specified Electrical Limits.
Like all other practical capacitors, multilayer
ceramic capacitors also have resistance and
inductance. A simplified schematic for the single
frequency equivalent circuit is shown in Figure 1.
At high frequency more complex models apply -
see KEMET SPICE models at www.kemet.com for
details.
2.
©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
67
Ceramic Surface Mount
CERAMIC CHIP CAPACITORS
Figure 1
IR
6.
Impedance:
Since the parallel resistance (IR) is normally very
high, the total impedance of the capacitor can be
approximated by:
Figure 3
ESL
ESR
C
C = Capacitance
ESL = Equivalent Series Inductance
ESR = Equivalent Series Resistance
IR = Insulation Resistance
2
2
Z=
ESR + (X - X )
L C
Where :
Z = Total Impedance
5.
Dissipation Factor:
Measured under same conditions as
capacitance. (See Table 3)
Dissipation factor (DF) is a measure of the losses in
a capacitor under AC application. It is the ratio of the
equivalent series resistance to the capacitive reac-
tance, and is usually expressed in percent. It is normal-
ly measured simultaneously with capacitance, and
under the same conditions. The vector diagram below
illustrates the relationship between DF, ESR and
impedance. The reciprocal of the dissipation factor is
called the “Q” or quality factor. For convenience, the
“Q” factor is often used for very low values of dissipa-
tion factor especially when measured at high frequen-
cies. DF is sometimes called the “loss tangent” or “tan-
gent ”, as shown in Figure 2.
ESR = Equivalent Series Resistance
X = Capacitive Reactance = 1/(2
πfC)
C
X = Inductive Reactance = (2
πf)
(ESL)
L
The variation of a capacitor's impedance with fre-
quency determines its effectiveness in many applica-
tions. At high frequency more detailed models apply -
see KEMET SPICE models for such instances.
7.
Figure 2
ESR
DF(%) =
ESR x 100
Xc
X
c
O
δ
Ζ
1
Xc
=
2 π
fC
Insulation Resistance:
Measured after 2 minutes electrification at 25°C and
rated voltage: Limits per Table 3.
Insulation Resistance is the measure of a capacitor
to resist the flow of DC leakage current. It is sometimes
referred to as “leakage resistance”. Insulation resis-
tance (IR) is the DC resistance measured across the
terminals of a capacitor, represented by the parallel
resistance (IR) shown in Figure 1. For a given dielectric
type, electrode area increases with capacitance, result-
ing in a decrease in the insulation resistance.
Consequently, insulation resistance limits are usually
specified as the “RC” (IR x C) product, in terms of ohm-
farads or megohm-micro-farads. The insulation resis-
tance for a specific capacitance value is determined by
dividing this product by the capacitance. However, as
the nominal capacitance values become small, the
insulation resistance calculated from the RC product
reaches values which are impractical. Consequently, IR
specifications usually include both a minimum RC prod-
uct and a maximum limit based on the IR calculated
Table 3 – Specified Electrical Limits
Parameter
Capacitance & Dissipation Factor: Measured at following
conditions:
C0G – 1kHz and 1 vrms if capacitance >1000 pF
1MHz and 1 vrms if capacitance
≤1000
pF
X7R/X5R/Y5V – 1kHz and 1 vrms* if capacitance
≤
10
µF
X7R/X5R/Y5V – 120Hz and 0.5 vrms if capacitance
>
10
µF
Z5U – 1kHz and 0.5 vrms
C0G
Temperature Characteristics
Z5U
X7R/X5R
Y5V
DF Limits:
**X5R
<25V
<25V
Cap
<564
≥564
50 - 200 volts
DF
25 volts
5.0%
16 volts
10.0%
6.3/10 volts
–
–
–
–
0.10%
0.10%
--------
--------
2.5%
3.5%
3.5%
5.0%
2.5%
5.0%
**
**
4.0%
4.0%
-------
5.0%
7.0%
7.0%
10.0%
Dielectric Strength: At 2.5 times rated DC voltage
Insulation Resistance (IR): At rated DC voltage, whichever
of the two is smaller. To get IR limit, divide MΩ−µF value by
the capacitance and compare to GΩ limit. Select the lower
of the two limits.
Temperature: Range,
°C
Capacitance Change (without DC voltage)
1,000 MΩ –
µF
or 100 GΩ
(100,000 MΩ)
-55 to +125
0
±
30 ppm/°C
Pass Subsequent IR Test
1,000 MΩ –
µF
or 100 GΩ
(100,000 MΩ)
X7R: -55 to +125
±
15%
X5R: -55 to +85
±
15%
100 MΩ –
µF
or 10 GΩ
(10,000 MΩ)
+10 to +85
+22% -56%
100 MΩ –
µF
or 10 G (≥16 volt)
50 MΩ –
µF
or 10G (
≤
10v)
(10,000 MΩ)
-30 to +85
+22% -82%
*Note: Some values measured at
1
⁄
2
volt, see X7R Table for specific details on pages 74 and 75.
68
©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
CERAMIC CHIP CAPACITORS
from that value. For example, a typical IR specification
might read “1,000 megohm-microfarads or 100
gigohms, whichever is less”. The DC leakage current
may be calculated by dividing the applied voltage by
the insulation resistance (Ohm's Law).
8.
Dielectric Withstanding Voltage:
250% of rated voltage for 5 seconds with current lim-
ited to 50mA at 25°C. Limits per Table 3.
Dielectric withstanding voltage (DWV) is the peak DC
voltage which a capacitor is designed to withstand
without damage for short periods of time. All KEMET
multilayer ceramic surface mount capacitors will with-
stand a DC test voltage of 2.5 x the rated voltage for 60
seconds.
KEMET specification limits for all electrical character-
istics at standard measurement conditions are shown in
Table 3. Variations in these properties caused by
changing conditions (temperature, voltage, frequency,
and time) are covered in the following sections.
Aging Rate:
Maximum % Capacitance Loss/Decade Hour
C0G - 0%
X7R - 2.0%
X5R - 5.0%
Z5U - 7.0%
Y5V - 7.0%
Actual rates may be lower. Consult factory for
details.
The capacitance of Class II and III dielectric changes
with time as well as with temperature, voltage and fre-
quency. The change with time is known as “aging”. It is
caused by gradual realignment of the crystalline struc-
ture of the ceramic dielectric material as it is cooled
below its Curie temperature, which produces a loss of
capacitance with time. The aging process is predictable
and follows a logarithmic decay.
The aging process is reversible. If the capacitor is
heated to a temperature above its Curie point for some
period of time, de-aging will occur and the capacitor will
regain the capacitance lost during the aging process.
The amount of de-aging depends on both the elevated
temperature and the length of time at that temperature.
Exposure to 150°C for one-half hour is sufficient to
return the capacitor to its initial value.
Because the capacitance changes rapidly immedi-
ately after de-aging, capacitance measurements are
usually delayed for at least 24-48 hours after the de-
aging process, which is often referred to as the “last
heat”. In addition, manufacturers utilize the aging rates
to set factory test limits which will bring the capacitance
within the specified tolerance at some future time, to
allow for customer receipt and use.
10.
Effect of Temperature:
Both capacitance and dissipation factor are affected
by variations in temperature. The maximum capacitance
change with temperature is defined by the temperature
characteristic.
However, this only defines an “envelope” bounded
by the upper and lower operating temperatures and the
minimum and maximum capacitance values. Within this
“envelope”, the variation with temperature depends
upon the specific dielectric formulation.
Insulation resistance decreases with increasing tem-
perature. Typically, the insulation resistance limit at
maximum rated temperature is 10% of the 25°C value.
11.
Effect of Voltage:
Certain high dielectric constant ceramic capacitors
may show variation in values of capacitance and dissi-
pation factor with various levels of applied AC and DC
voltages. Such variation is a natural characteristic of
ceramic capacitors, and should be considered by the
circuit designer.
In general, ceramic capacitors with the lowest dielec-
tric constant (C0G or NP0) are extremely stable, and
show little or no variation in capacitance and/or dissipa-
tion factor. On the other hand, ceramic capacitors with
the highest dielectric constant (Z5U & Y5V) may show
significant variation, particularly in capacitance. Other
dielectric formulations such as X7R and X5R will show
less variation than Y5V, but more than C0G.
The application of AC voltages in the range of 10 to
20 VAC tends to increase the values of both the capaci-
tance and dissipation factor, while higher AC voltages
tend to produce decreases in both.
However, the variation of capacitance with applied
DC is the parameter of most interest to design engi-
neers. Figure 8 shows typical variation of capacitance
with applied DC voltage for some standard dielectrics.
As can be seen, the decrease in capacitance is greatest
for the Y5V dielectric (the C0G is not plotted, since it
would not have a perceptible capacitance nor dissipa-
9.
Figure 8 - Typical Variation of Capacitance with Applied DC Voltage
tion factor change.)
More detailed modelling information on the effect of
various voltages on specific capacitor ratings can be
obtained by use of the KEMET SPICE models, available
for free downloading at our website (www.kemet.com).
12.
Effect of Frequency:
Frequency affects both capacitance and dissipation
factor. Typical curves for KEMET multilayer ceramic
capacitors are shown in Figures 4, 5, 6 and 7.
The variation of impedance with frequency is an
important consideration in the application of multilayer
ceramic capacitors. Total impedance of the capacitor is
©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
69
Ceramic Surface Mount
CERAMIC CHIP CAPACITORS
the vector summation of the capacitive reactance, the
inductive reactance, and the ESR, as illustrated in
Figure 2. As frequency increases, the capacitive reac-
tance decreases. However, the series inductance (L)
shown in Figure 1 produces some inductive reactance,
which increases with frequency. At some frequency, the
impedance ceases to be capacitive and becomes
inductive. This point, at the bottom of the V-shaped
impedance versus frequency curves, is the self-reso-
nant frequency. At the self-resonant frequency, the
reactance is zero, and the impedance consists of the
ESR only. At high frequency more detailed models
apply - See KEMET SPICE models for such instances.
Typical impedance versus frequency curves for
KEMET multilayer ceramic capacitors are shown in
Figures 4, 5, 6 and 7
.
dissipation. As with any practical device, multilayer
ceramic capacitors also possess an inherent, although
low, failure rate when operated within rated conditions.
The primary failure mode is by short-circuit or low insu-
lation resistance, resulting from cracks or from dielectric
breakdown at a defect site. KEMET monitors reliability
with a periodic sampling program for selected values.
Results are available in our FIT (Failure in Time) report
for commercial chips.
21.
Storage and Handling:
Ceramic chip capacitors should be stored in normal
working environments. While the chips themselves are
quite robust in other environments, solderability will be
degraded by exposure to high temperatures, high
humidity, corrosive atmospheres, and long term stor-
age. In addition, packaging materials will be degraded
by high temperature – reels may soften or warp, and
tape peel force may increase. KEMET recommends
that maximum storage temperature not exceed 40
degrees C, and maximum storage humidity not exceed
70% relative humidity. In addition, temperature fluctua-
tions should be minimized to avoid condensation on
the parts, and atmospheres should be free of chlorine
and sulfur bearing compounds. For optimized solder-
ability, chip stock should be used promptly, preferably
within 1.5 years of receipt.
ENVIRONMENTAL AND PHYSICAL
13.
Thermal Shock:
EIA-198, Method 202, Condition B (5 cycles
-55° to + 125°C).
Life Test:
EIA-198, Method 201, 1000 hours at 200%
*
of rated
voltage at 125°C. (Except 85°C for Z5U, Y5V
& X5R).
See Table 4 on page 71 for limits.
*Note: 150% of rated voltage for selected high capacitance X5R values. Please contact factory.
14.
15.
Humidity Test:
EIA-198, Method 206, ( Except 1000 hours,85°C,
85% RH, Rated Voltage).
See Table 4 on page 71 for limits.
Moisture Resistance:
EIA-198, Method 204, Condition B (20 cycles with
50 volts applied.
See Table 4 on page 71 for limits.
Solderability:
EIA-198, Method 301 (245°, 5 secs, Sn62 solder)
95% smooth solder on terminations. See page 14
for recommended profiles.
Resistance to Soldering Heat:
EIA-198, Method 302, Condition B (260°C, 10 sec-
onds) no leaching of nickel barrier.
Terminal Strength:
EIA-198, Method 303, Condition D .
MISAPPLICATION
22.
Ceramic capacitors, like any other capacitors, may fail if
they are misapplied. Some misapplications include
mechanical damage, such as impact or excessive flex-
ing of the circuit board. Others include severe mounting
or rework cycles that may also introduce thermal shock.
Still others include exposure to excessive voltage, cur-
rent or temperature. If the dielectric layer of the capaci-
tor is damaged by misapplication, the circuit may fail.
The electrical energy of the circuit can be released as
heat, which may damage the circuit board and other
components as well.
16.
17.
18.
ADDITIONAL INFORMATION
23.
Detailed application information can be found in KEMET
Engineering Bulletins.
F-2100
F-2102
F-2105
F-2103
F-2110
F-2111
Surface Mount-Mounting Pad
Dimensions and Considerations
Reflow Soldering Process
Wave Solder Process
Surface Mount Repair
Capacitance Monitoring while Flex Testing
Ceramic Chip Capacitors “Flex Cracks” -
Understanding and Solutions
19.
RELIABILITY
20.
A well constructed multilayer ceramic capacitor chip is
extremely reliable and, for all practical purposes, has no
wearout mechanism when used within the maximum
voltage and temperature ratings. Most failures occur as
a result of mechanical or thermal damage during
mounting on the board, or during subsequent testing.
Capacitor failure may also be induced by sustained
operation at voltages that exceed the rated DC voltage,
voltage spikes or transients that exceed the dielectric's
voltage capability, sustained operation at temperatures
above the maximum rated temperature, internal
defects, or excessive temperature rise due to power
For analysis of high frequency applications, KEMET
has SPICE models of most chip capacitors. Models
may be downloaded from KEMET’s website
www.kemet.com.
70
Additional information is also available - See
your KEMET representative for details or post your
questions to KEMET's homepage on the web
http://www.kemet.com.
©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
CERAMIC CHIP CAPACITORS
TABLE 4 – ENVIRONMENTAL LIMITS
Cap Shift (% or pf,
whichever is greater)
IR
DF (%)
Post Life/
(GΩ or
ΩF)
Post Life/
Initial whichever is Hum/Moisture
Hum/Moisture
DF (%)
Resistance
less
Resistance
IR (GΩ or
ΩF)
whichever is less
Post Life/
Hum/Moisture
Resistance
Body
Rated DC
Voltage
C0G
X7R
X5R
200
∗
100
50
25
16
200
∗
100
50
25
16
6.3/10
50V all cap values
25V all cap values
_
<25<564 cap value
>564 cap value
Z5U
Y5V
100
50
25
100
50
25
16
6.3/10
0.1
0.1
0.1
0.1
0.1
2.5
2.5
2.5
3.5
3.5
5.0
2.5
5.0
5.0
10.0
4.0
4.0
4.0
5.0
5.0
7.0
7.0
10.0
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
100/1000
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/50
0.5
0.5
0.5
0.5
0.5
3.0
3.0
3.0
5.0
5.0
7.5
3.0
7.5
7.5
12.0
5.0
5.0
7.5
7.5
7.5
10.0
10.0
15.0
0.3% or
±
0.25 pf
0.3% or
±
0.25 pf
0.3% or
±
0.25 pf
0.3% or
±
0.25 pf
0.3% or
±
0.25 pf
±
20%
±
20%
±
20%
±
20%
±
20%
±
20%
±
20%
±
20%
±
20%
±
20%
±
30%
±
30%
±
30%
±
30%
±
30%
±
30%
±
30%
±
30%
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
10/100
1/10
1/10
1/10
1/10
1/10
1/10
1/10
1/5
*200 Volt limits not currently included in EIA-198.
PERFORMANCE CURVES
EFFECT OF FREQUENCY
(See SPICE models for specific ratings.)
Impedance (Ohms)
100,000
10,000
1,000
100
10
1
0.1
0.01
0.001
0.1
0.3
1
3
2225
103
1206
102
0603
101
0805
101
Impedance (Ohms)
1,000
100
10
1
0805
103
0805
104
0603
103
1206
103
0.1
1206
104
10
30
Frequency (MHz)
100
300
1,000
0.01
0.1
0.3
1
3
30
10
Frequency (MHz)
100
300
1,000
FIGURE 4. Impedance versus Frequency C0G Dielectric
Impedance (Ohms)
30
10
3
FIGURE 5
Impedance versus Frequency X7R Dielectric
Impedance (Ohms)
10
1
0.1
1
0.3
0.1
0.03
0.1
0.3
1
3
1206
105
Y5V
0805
104
Y5V
0603
104
Y5V
1206
104
Z5U
0.01
0.001
0.1
1
10
Frequency (MHz)
AC
AC
100
AC
AC
1000
10
30
Frequency (MHz)
100
300
1,000
FIGURE 6. Impedance versus Frequency Z5U/Y5V Dielectric
C0603C105K8P
C0805C106K9P
C1206C105K8P
C1206C106K8P
FIGURE 7.
Impedence versus Frequency X5R Dielectric
©KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
71
Ceramic Surface Mount
工业自动化与控制
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
