AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
Features
-
Drive Strength (DS) Option: Full, 1/2, 1/4 and 3/4
-
Auto Temperature Compensated Self Refresh
(Auto TCSR)
-
Partial Array Self Refresh (PASR) option: Full, 1/
2, 1/4, 1/8 and 1/16
-
Deep Power Down (DPD) mode
-
Programmable Power Reduction Feature by patial
array activation during Self-Refresh
-
Operating Temperature Range
-
4 banks x 8Mbit x 16 organization
-
4 banks x 4Mbit x 32 organization
-
High speed data transfer rates up to 166 MHz
-
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
-
Single Pulsed RAS Interface
-
Data Mask for Read/Write Control
-
Four Banks controlled by BA0 & BA1
Commercial (-25°C to 85°C)
-
Programmable CAS Latency: 2, 3
Industrial (-40°C to +85°C)
-
Programmable Wrap Sequence:
Sequential or Interleave
-
Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
-
Multiple Burst Read with Single Write Operation
-
Automatic and Controlled Precharge Command
-
Random Column Address every CLK (1-N Rule)
-
Power Down Mode and Clock Suspend Mode
-
Auto Refresh and Self Refresh
-
Refresh Interval:
8192 cycles/64 ms
-
Available in 54-ball (32M x16) and 90-ball (16M x32)FBGA
-
VDD=1.8V, VDDQ=1.8V
-
LVTTL Interface
Table 1. Key Specifications
tCK(3)
tAC(3)
tRAS
tRC
AS4C32M16MS/AS4C16M32MS
Clock Cycle time(min.)
Access time from CLK (max.)
Row Active time(min.)
Row Cycle time(min.)
-6/7
6/7.5 ns
5/5.4 ns
42/45 ns
60/67.5 ns
Table 2. Ordering Information
Part Number
AS4C32M16MS-7BCN
AS4C32M16MS-6BIN
AS4C16M32MS-7BCN
AS4C16M32MS-6BIN
Org
32Mx16
32Mx16
16Mx32
16Mx32
Temperature
Commercial
-25°C to +85°C
Industrial
-40°C to +85°C
Commercial
-25°C to +85°C
Industrial
-40°C to +85°C
MaxClock (MHz)
133
166
133
166
Package
54-ball FBGA
54-ball FBGA
90-ball FBGA
90-ball FBGA
Confidential
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Rev.1.0 June 2016
AS4C32M16MS-7BCN / AS4C32M16MS-6BIN
AS4C16M32MS-7BCN / AS4C16M32MS-6BIN
The
AS4C32M16MS
/ AS4C16M32MS
is a four bank Synchronous DRAM organized as 4 banks x
8Mbit x 16 and 4 banks x 4Mbit x 32. The
AS4C32M16MS
/ AS4C16M32MS
achieves high speed data
transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. All of the control, address, data input and output circuits
are synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at
higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 MHz is
possible depending on burst length, CAS latency and speed grade of the device.
Description
Signal Pin Description
Pin
CLK
CKE
CS
Type
Input
Input
Input
Signal
Pulse
Level
Pulse
Polarity
Positive
Edge
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous
operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
—
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
and A0-A13 defines the row address (RA0-RA13) for 16Mx32 reduced page size when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
for 32Mx16, A0-A8 defines the column address (CA0-CA8) for 16Mx32 and A0-A7 de-
fines tthe column address (CA0-CA7) for 16Mx32 reduced page size when sampled at
the rising clock edge.
In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1
to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are
used to define which bank to precharge.
Selects which bank is to be active.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
RAS, CAS
WE
A0 - A13
Input
Input
Pulse
Level
BA0,
BA1
DQx
LDQM
UDQM
(DM0~3)
Input
Input
Output
Input
Level
Level
Pulse
—
—
Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high. If it’s high, LDM corresponds to DQ0-DQ7, and UDM corresponds to data
on DQ8-DQ15 in 32Mx16. DM0 corresponds to DQ0-DQ7, DM1 corresponds to data on
DQ8-DQ15, DM2 corresponds to DQ16-DQ23, and DM3 corresponds to data on DQ24-
DQ31 in 16Mx32.
Power and ground for the input buffers and the core logic.
VDD, VSS
VDDQ
VSSQ
NC
Supply
Supply
Input
—
—
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
No connect.
Confidential
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Rev.1.0 June 2016
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