Ultra Series
™
Crystal Oscillator
Si542 Data Sheet
Ultra Low Jitter Quad Any-Frequency XO (125 fs), 0.2 to 1500
MHz
The Si542 Ultra Series
™
oscillator utilizes Silicon Laboratories’ advanced 4
th
gen-
eration DSPLL
®
technology to provide an ultra-low jitter, low phase noise clock at
four selectable frequencies. The device is factory-programmed to provide any four
selectable frequencies from 0.2 to 1500 MHz with <1 ppb resolution and maintains
exceptionally low jitter for both integer and fractional frequencies across its operat-
ing range. The Si542 offers excellent reliability and frequency stability as well as
guaranteed aging performance. On-chip power supply filtering provides industry-
leading power supply noise rejection, simplifying the task of generating low jitter
clocks in noisy systems that use switched-mode power supplies. Offered in indus-
try-standard 3.2x5 mm and 5x7 mm footprints, the Si542 has a dramatically simpli-
fied supply chain that enables Silicon Labs to ship custom frequency samples 1-2
weeks after receipt of order. Unlike a traditional XO, where a different crystal is re-
quired for each output frequency, the Si542 uses one simple crystal and a DSPLL
IC-based approach to provide the desired output frequencies. This process also
guarantees 100% electrical testing of every device. The Si542 is factory-configura-
ble for a wide variety of user specifications, including frequency, output format,
and OE pin location/polarity. Specific configurations are factory-programmed at
time of shipment, eliminating the long lead times associated with custom oscilla-
tors.
Pin Assignments
FS1
OE/NC
KEY FEATURES
• Available with any four selectable
frequencies from 200 kHz to 1500 MHz
• Very low jitter: 125 fs Typ RMS
(12 kHz – 20 MHz)
• Excellent PSRR and supply noise immunity:
–80 dBc Typ
• 10 ppm stability option (-40 to 85 °C)
• 3.3 V, 2.5 V and 1.8 V V
DD
supply operation
from the same part number
• LVPECL, LVDS, CML, HCSL, CMOS, and
Dual CMOS output options
• 3.2×5, 5x7 mm package footprints
• Samples available with 1-2 week lead times
APPLICATIONS
• 100G/200G/400G OTN, coherent optics
• 10G/25G/40G/100G Ethernet
• 3G-SDI/12G-SDI/24G-SDI broadcast video
• Servers, switches, storage, NICs, search
acceleration
• Test and measurement
• Clock and data recovery
• FPGA/ASIC clocking
1
2
3
7
6
5
4
VDD
CLK-
CLK+
NC/OE
GND
8
FS0
(Top View)
Pin #
1, 2
3
4
5
6
7
8
Descriptions
Selectable via ordering option
OE = Output enable; NC = No Connect
GND = Ground
CLK+ = Clock output
CLK- = Complementary clock output. Not used for CMOS.
NVM
OSC
Fixed
Frequency
Crystal
Frequency
Flexible
DSPLL
DCO
Low
Noise
Driver
Digital
Phase
Detector
Phase Error
Cancellation
Phase Error
Fractional
Divider
Digital
Loop
Filter
Flexible
Formats,
1.8V – 3.3V
Operation
VDD = Power supply
FS1 = Frequency Select 1
FS0 = Frequency Select 0
Control
Power Supply Regulation
OE, Frequency Select
(Pin Control)
Built-in Power Supply
Noise Rejection
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Rev. 0.75
Si542 Data Sheet
Ordering Guide
1. Ordering Guide
The Si542 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to
www.silabs.com/oscillators
to access
this tool and for further ordering instructions.
XO Series
542
Description
Quad Frequency
Temp Stability
A
B
Total Stability
2
±
20 ppm
±
10 ppm
±
50 ppm
±
25 ppm
A
B
Package
5x7 mm
3.2x5 mm
G
Temperature Grade
-40 to 85 °C
542
Signal Format
LVPECL
LVDS
CMOS
CML
HCSL
Dual CMOS
(In-Phase)
Dual CMOS
(Complementary)
Custom
1
A
A
A
OE
Pin
Pin 1
Pin 1
Pin 2
Pin 2
-
-
-
-
-
-
A
B
G
R
Order
VDD Range
Option
2.5, 3.3 V
A
1.8, 2.5, 3.3 V
B
1.8, 2.5, 3.3 V
C
1.8, 2.5, 3.3 V
D
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
1.8, 2.5, 3.3 V
E
F
G
X
Device Revision
OE Polarity
Active High
Active Low
Active High
Active Low
Frequency Code
3
Reel
Tape and Reel
Coil Tape
A
B
C
D
R
<Blank>
Description
Four unique frequencies can be specified
within the supported range of the selected
signal format. The frequencies can be
arranged in any order from FS[1:0]=00 to
FS[1:0]=11. A six digit numeric code will be
assigned for the specific combination of
frequencies.
xxxxxx
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 °C.
3. Create custom part numbers at
www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ)
Oscillator Phase Noise Lookup Utility
Quality and Reliability
Development Kits
www.silabs.com/Si542-FAQ
www.silabs.com/oscillator-phase-noise-lookup
www.silabs.com/quality
www.silabs.com/oscillator-tools
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Rev. 0.75 | 2
Si542 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Electrical Specifications
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Temperature Range
Frequency Range
Symbol
T
A
F
CLK
LVPECL, LVDS, CML
HCSL
CMOS, Dual CMOS
Supply Voltage
V
DD
3.3 V
2.5 V
1.8 V
Supply Current
I
DD
LVPECL (output enabled)
LVDS/CML (output enabled)
HCSL (output enabled)
CMOS (output enabled)
Dual CMOS (output enabled)
Tristate Hi-Z (output disabled)
Temperature Stability
Frequency stability Grade A
Frequency stability Grade B
Total Stability
1
F
STAB
Frequency stability Grade A
Frequency stability Grade B
Rise/Fall Time
(20% to 80% V
PP
)
T
R
/T
F
LVPECL/LVDS/CML
CMOS / Dual CMOS, (C
L
= 5 pF)
HCSL, F
CLK
>50 MHz
Duty Cycle
Output Enable (OE)
Frequency Select (FS0, FS1)
2
D
C
V
IH
V
IL
T
D
T
E
T
FS
Powerup Time
LVPECL Output Option
3
t
OSC
V
OC
V
O
Output Disable Time, F
CLK
> 10 MHz
Output Enable Time, F
CLK
> 10 MHz
Settling Time after FS Change
Time from 0.9 × V
DD
until output fre-
quency (F
CLK
) within spec
Mid-level
Swing (diff)
All formats
Test Condition/Comment
Min
–40
0.2
0.2
0.2
3.135
2.375
1.71
—
—
—
—
—
—
–20
–10
–50
–25
—
—
—
45
0.7 × V
DD
—
—
—
—
—
V
DD
– 1.42
1.1
Typ
—
—
—
—
3.3
2.5
1.8
100
75
80
74
80
64
—
—
—
—
—
0.5
—
—
—
—
—
—
—
—
—
—
Max
85
1500
400
250
3.465
2.625
1.89
132
111
125
108
125
100
20
10
50
25
350
1.5
550
55
—
0.3 × V
DD
3
20
10
10
V
DD
– 1.25
1.9
Unit
ºC
MHz
MHz
MHz
V
V
V
mA
mA
mA
mA
mA
mA
ppm
ppm
ppm
ppm
ps
ns
ps
%
V
V
µs
µs
ms
ms
V
V
PP
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Rev. 0.75 | 3
Si542 Data Sheet
Electrical Specifications
Parameter
LVDS Output Option
4
Symbol
V
OC
Test Condition/Comment
Mid-level (2.5 V, 3.3 V VDD)
Mid-level (1.8 V VDD)
V
O
HCSL Output Option
5
V
OH
V
OL
V
C
CML Output Option
(AC-Coupled)
CMOS Output Option
V
O
V
OH
V
OL
Swing (diff)
Output voltage high
Output voltage low
Crossing voltage
Swing (diff)
I
OH
= 8/6/4 mA for
3.3/2.5/1.8 V VDD
I
OL
= 8/6/4 mA for
3.3/2.5/1.8 V VDD
Min
1.125
0.8
0.5
660
–150
250
0.6
0.85 × V
DD
—
Typ
1.20
0.9
0.7
750
0
350
0.8
—
—
Max
1.275
1.0
0.9
850
150
550
1.0
—
0.15 × V
DD
Unit
V
V
V
PP
mV
mV
mV
V
PP
V
V
Notes:
1. Total Stability includes temperature stability, initial accuracy, load pulling, VDD variation, and aging for 20 yrs at 70 ºC.
2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low. FS0 and FS1 pins
each include a 50 kΩ pull-up to VDD. NC (No Connect) pins include a 50 kΩ pull-down to GND.
3. 50 Ω to V
DD
– 2.0 V.
4. R
term
= 100 Ω (differential).
5. 50 Ω to GND.
Table 2.2. Clock Output Phase Jitter and PSRR
V
DD
= 1.8 V, 2.5 or 3.3 V ± 5%, T
A
= –40 to 85 ºC
Parameter
Phase Jitter (RMS, 12kHz - 20MHz)
1
3.2 x 5 mm, F
CLK
≥ 100 MHz
Phase Jitter (RMS, 12kHz - 20MHz)
1
5 x 7 mm, F
CLK
≥ 100 MHz
Spurs Induced by External Power Supply
Noise, 50 mVpp Ripple. LVDS 156.25 MHz
Output
PSRR
Symbol
ϕ
J
Test Condition/Comment
Differential Formats
CMOS, Dual CMOS
ϕ
J
Differential Formats
CMOS, Dual CMOS
100 kHz sine wave
200 kHz sine wave
500 kHz sine wave
1 MHz sine wave
Note:
1. Guaranteed by characterization. Jitter inclusive of any spurs.
Min
—
—
—
—
—
—
—
—
Typ
125
200
150
200
-83
-83
-82
-85
Max
200
—
200
—
—
—
—
—
dBc
Unit
fs
fs
fs
fs
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Rev. 0.75 | 4
Si542 Data Sheet
Electrical Specifications
Table 2.3. 3.2 x 5 mm Clock Output Phase Noise (Typical)
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Offset Frequency (f)
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
156.25 MHz LVDS
–110
–121
–132
–139
–151
–160
–161
156.25 MHz
LVPECL
–113
–123
–133
–139
–151
–162
–163
200 MHz LVDS
–107
–120
–130
–137
–149
–161
–162
200 MHz
LVPECL
–110
–120
–130
–137
–149
–166
–167
644.53125 MHz LVDS
–99
–109
–121
–127
–138
–155
–157
644.53125 MHz
LVPECL
–100
–110
–119
–127
–138
–156
–157
dBc/Hz
Unit
dBc/Hz
Unit
Phase jitter measured with Agilent E5052 using a differential-to-single ended converter (balun or buffer). Measurements collected for
>700 commonly used frequencies. Phase noise plots for specific frequencies are available using our free, online Oscillator Phase Noise
Lookup Tool at
www.silabs.com/oscillators.
Figure 2.1. Phase Jitter vs. Output Frequency
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Rev. 0.75 | 5
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