CXD2932AGA-2
GPS Base Band LSI
Description
The CXD2932AGA-2 is a dedicated LSI for the GPS
(Global Positioning System) satellite-based position
measurement system.
This LSI contains a 32-bit RISC CPU, satellite
tracking circuit, 2M-bit mask ROM, RAM, UART,
interval timer, and others.
This LSI, used together with the RF LSI, enables the
configuration of a 2-chip system capable of measuring
its position anywhere on the globe.
Features
•
16-channel GPS receiver capable of
simultaneously receiving 16 satellites
•
Supports differential GPS
— Conforms to RTCM SC-104 Ver. 2.1
— Supports DARC
All-in-view measurement
Timer supporting GPS time
32-bit RISC CPU
256K-byte program ROM
40K-byte RAM
Power management function
1PPS supported
2-channel UART
4-channel interval timer
16-bit general-purpose I/O port
12-bit successive approximation system A/D
converter (4-channel analog switch)
Absolute Maximum Ratings
•
Supply voltage
V
DD
V
SS
– 0.5 to 4.6
•
Input voltage
V
I
V
SS
– 0.5 to V
DD
+ 0.5
144 pin LFLGA (Plastic)
V
V
•
Output voltage
V
O
V
SS
– 0.5 to V
DD
+ 0.5 V
•
Operating temperature
Topr
–40 to +85
°C
•
Storage temperature
Tstg
–50 to +150
°C
•
•
•
•
•
•
•
•
•
•
•
Recommended Operating Conditions
•
Supply voltage
V
DD
3.0 to 3.6
•
Operating temperature
Topr
–40 to +85
Input/Output Pin Capacitance
•
Input capacitance
C
IN
9 (Max.)
•
Output capacitance C
OUT
11 (Max.)
•
I/O capacitance
C
I/O
11 (Max.)
V
°C
pF
pF
pF
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E03202A37
CXD2932AGA-2
Performance
•
16-channel GPS receiver
•
32-bit RISC CPU
•
Receiver frequency: 1575.42MHz (L1 band, CA code)
•
Reception sensitivity
Tracking sensitivity: –145dBm or less (typ.) when using the antenna of 25dBi, NF = 2dB and the RF
amplifier with the 25dB gain for the RF block
∗
Reference data using the Sony's reference board.
This value is not guaranteed, depending on the conditions.
•
Time to First Fix (time until initial measurement after power-on)
Cold Start (without both ephemeris and almanac): 27 to 58s
Warm Start (without ephemeris with almanac):
23 to 45s
Hot Start (with both ephemeris and almanac):
6 to 17s
∗
Reference data with elevation angle of 5° or more and no interception environment on June, 2002.
Positioning time with 90% possibility.
These values are not guaranteed, depending on the conditions.
•
Positioning accuracy
2DRMS: approx. 5m
∗
Reference data with elevation angle of 5° or more and no interception environment on June, 2002.
This value is not guaranteed, depending on the conditions.
•
Measurement data update time: 1s
•
Communication format: Sony Binary
NMEA-0183
Customized NMEA (9600bps)
•
All-in-view
–2–
CXD2932AGA-2
Block Diagram
JTAG (ARM-CORE)
JTAG
TCXO/XTCXO (OSC)
CLKI/CLKO (OSC)
CLKOUT
ARM-CORE
(A7TDMI)
ARM7TDMI
ARBITER
(ARBITER)
XPWRS
XRS
DECODER
(DECODER)
TIC
(TIC)
XGBE
XROMI
ROMW
CLKS[2:0]
TEST[1:0]
XWE[3:0]
XCS[3:0]
XOE
TAP-CTL
(DFTC6)
CLKGEN
(CLKGEN)
BIST (SRAM)
SCAN
9 to 18MHz (ARM)
18MHz (TCXO)
6MHz (USB)
System
(SYS_REG)
Interrupt
(INT_CNTL)
SSD1: 17ch
(SSD1)
XINT[1:0]
IFI/IFO(OSC)
REFCK
A/D
Timer: 3ch
(TMITU)
AHB
APB
SRAM: 40KB
(DMEM_40KB)
ROM: 256KB
(IMEM_M)
32k-Timer
(ITU32K)
UART: 2ch
(DUART)
USB/DRV
(USB)
PORT
(PORT)
ADDR: 20 bit
DATA: 32 bit
RXD[1:0]
TXD[1:0]
USB-I/F
ADDR: 32 bit
DATA: 32 bit
APB-Bridge
(APBIF)
ADDR: 20 bit
DATA: 32 bit
ED[31:0]
EA[19:0]
BUS-I/F
(SMI)
PORT[15:0]
AHB: AMBA High Performance Bus
APB: AMBA Peripheral Bus
TIC: Test Interface Controller
–3–
CXD2932AGA-2
Pin Configuration
(Top View)
70
XWE2
75
ROMW
78
V
DD
3
81
ED4
83
ED6
86
ED8
87
ED9
90
V
DD
4
91
ED12
94
ED15
95
ED16
98
ED18
100
ED20
103
ED22
106
ED25
67
XINT1
71
XWE3
74
XROMI
77
ED1
79
ED2
82
ED5
85
ED7
89
ED11
92
ED13
96
V
SS
5
99
ED19
102
V
DD
5
104
ED23
107
ED26
111
ED29
64
XRS
68
XWE0
72
V
SS
3
73
XOE
76
ED0
80
ED3
84
V
SS
4
88
ED10
93
ED14
97
ED17
101
ED21
105
ED24
108
V
SS
6
110
ED28
114
V
DD
6
62
GBE
66
V
DD
2
69
XWE1
59
CLKO
63
XPWRS
65
58
CLKI
60
V
SS
2
61
55
CLKS0
56
54
V
DD
1
53
51
V
SS
1
49
50
AVS3
46
AVS1
44
AVS2
47
AVD3
43
VRT
40
VIN2
45
AVD1
41
VIN3
37
AVD2
42
VRB
38
VIN0
36
V
DD
11
33
TDI
29
V
SS
11
25
TEST0
21
RXD1
16
39
VIN1
35
TMS
32
TCK
30
34
TDO
31
TRST
28
CCKO
26
CLKS1 XTCXO USBDP
57
52
48
XINT0 CLKOUT CLKS2
TCXO USBDM
REFCK TEST1
27
CCKI
24
IFO
20
TXD1
17
23
IFI
22
V
DD
10
19
RXD0
18
PORT14 PORT15 TXD0
12
13
15
PORT11 PORT12 V
SS
10
8
V
DD
9
4
10
14
PORT9 PORT13
7
11
PORT4 PORT7 PORT10
1
V
SS
9
109
ED27
113
ED31
117
EA2
112
ED30
115
EA0
119
EA4
116
EA1
118
EA3
122
EA6
120
V
SS
7
121
EA5
123
EA7
124
EA8
125
EA9
126
V
DD
7
129
EA12
128
EA11
127
EA10
133
EA15
132
V
SS
8
130
EA13
137
EA19
135
EA17
131
EA14
141
XCS2
138
V
DD
8
134
EA16
144
5
9
PORT5 PORT8
2
6
PORT1 PORT2 PORT6
140
XCS1
136
EA18
143
3
PORT0 PORT3
139
XCS0
142
XCS3
–4–
CXD2932AGA-2
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Symbol
V
SS
9
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
V
DD
9
PORT8
PORT9
PORT10
PORT11
PORT12
PORT13
V
SS
10
PORT14
PORT15
TXD0
RXD0
TXD1
RXD1
V
DD
10
IFI
IFO
TEST0
TEST1
CCKI
CCKO
V
SS
11
REFCK
TRST
TCK
TDI
TDO
TMS
V
DD
11
AVD2
I/O
—
V
SS
Description
I/O/Z I/O port 2 (See the Application Circuit for setting.)
I/O/Z I/O port 3 (See the Application Circuit for setting.)
I/O/Z I/O port 4 (See the Application Circuit for setting.)
I/O/Z I/O port 5 (See the Application Circuit for setting.)
I/O/Z I/O port 6 (See the Application Circuit for setting.)
I/O/Z I/O port 7 (See the Application Circuit for setting.)
—
V
DD
I/O/Z I/O port 8 (See the Application Circuit for setting.)
I/O/Z I/O port 9 (See the Application Circuit for setting.)
I/O/Z I/O port 10 (See the Application Circuit for setting.)
I/O/Z I/O port 11 (See the Application Circuit for setting.)
I/O/Z I/O port 12 (See the Application Circuit for setting.)
I/O/Z I/O port 13 (See the Application Circuit for setting.)
—
V
SS
I/O/Z I/O port 14
I/O/Z I/O port 15
O/Z
I
O/Z
I
—
I
O
I
I
I
O
—
I
I
I
I
O/Z
I
—
—
UART transmission data (CH0)
UART reception data (CH0)
UART transmission data (CH1)
UART reception data (CH1)
V
DD
IF signal binary conversion circuit
Test (Low level fixed)
Test (Low level fixed)
Timer oscillation circuit (32.768kHz ± 100ppm)
V
SS
Test (Low level fixed)
Test (Open)
Test (Open)
Test (Open)
Test
Test (Open)
V
DD
A/D converter V
DD
–5–
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