SiC638
www.vishay.com
Vishay Siliconix
50 A VRPower
®
Integrated Power Stage
DESCRIPTION
The SiC638 are integrated power stage solutions optimized
for synchronous buck applications to offer high current, high
efficiency, and high power density performance. Packaged
in Vishay’s proprietary 5 mm x 5 mm MLP package, SiC638
enables voltage regulator designs to deliver up to 50 A
continuous current per phase.
The internal power MOSFETs utilizes Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
The SiC638 incorporate an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, an integrated bootstrap Schottky diode,
a thermal warning (THWn) that alerts the system of
excessive junction temperature, and zero current detection
to improve light load efficiency. The drivers are also
compatible with a wide range of PWM controllers and
supports tri-state PWM, 3.3 V / 5 V PWM logic.
FEATURES
• Thermally enhanced PowerPAK
®
MLP55-31L
package
• Vishay’s Gen IV MOSFET technology and a low
side MOSFET with integrated Schottky diode
• Delivers up to 50 A continuous current
• High efficiency performance
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 19 V input stage
• 3.3 V / 5 V PWM logic with tri-state and hold-off
• Zero current detect control for light load efficiency
improvement
• Low PWM propagation delay (< 20 ns)
• Faster disable
• Thermal monitor flag
• Under voltage lockout for V
CIN
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for computing, graphics card and
memory
• Intel IMVP-8 VRPower delivery
-V
CORE
, V
GRAPHICS
, V
SYSTEM AGENT
Skylake, Kabylake
platforms
-V
CCGI
for Apollo Lake platforms
• Up to 24 V rail input DC/DC VR modules
TYPICAL APPLICATION DIAGRAM
5V
Input
V
DRV
NC
V
IN
BOOT
PHASE
SW
Output
V
CIN
ZCD_EN#
PWM
controller
DSBL#
PWM
THWn
Gate
driver
Fig. 1 - SiC638 and SiC638A Typical Application Diagram
C
GND
GL
P
GND
S18-0299-Rev. A, 19-Mar-18
Document Number: 76582
1
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC638
www.vishay.com
PINOUT CONFIGURATION
Vishay Siliconix
31 30 29 28 27 26 25 24
33
GL
24 25 26 27 28 29 30 31
1 PWM
GL
PWM 1
ZCD_EN# 2
V
CIN
3
C
GND
4
BOOT 5
N.C. 6
PHASE 7
V
IN
8
9
V
IN
10 11
V
IN
V
IN
VIN
CGND
G
L
23 V
SWH
22 V
SWH
21 V
SWH
20 V
SWH
PGND
19 V
SWH
18 V
SWH
17 V
SWH
16 V
SWH
V
SWH
23
V
SWH
22
V
SWH
21
V
SWH
20
V
SWH
19
V
SWH
18
V
SWH
17
V
SWH
16
35
P
GND
DSBL#
THWn
P
GND
V
DRV
SW
SW
SW
GL
P
GND
P
GND
P
GND
P
GND
V
IN
V
IN
Top view
Bottom view
Fig. 2 - SiC638 and SiC638A Pin Configuration
PIN CONFIGURATION
PIN NUMBER
1
2
3
4, 32
5
6
7
8 to 11, 34
12 to 15, 28, 35
16 to 26
27, 33
29
30
31
NAME
PWM
ZCD_EN#
V
CIN
C
GND
BOOT
N.C.
PHASE
V
IN
P
GND
SW
GL
V
DRV
THWn
DSBL#
PWM input logic
The ZCD_EN# pin enables or disables diode emulation. When ZCD_EN# is LOW, diode emulation is
allowed. When ZCD_EN# is HIGH, continuous conduction mode is forced
Supply voltage for internal logic circuitry
Signal ground
High side driver bootstrap voltage
Not connected internally, can be left floating or connected to ground
Return path of high side gate driver
Power stage input voltage. Drain of high side MOSFET
Power ground
Phase node of the power stage
Low side MOSFET gate signal
Supply voltage for internal gate driver
Thermal warning open drain output
Disable pin. Active low
FUNCTION
ORDERING INFORMATION
PART NUMBER
SiC638CD-T1-GE3
SiC638ACD-T1-GE3
SiC638DB
PACKAGE
PowerPAK MLP55-31L
PowerPAK MLP55-31L
MARKING CODE
SiC638
SiC638A
Reference board
OPTION
5 V PWM optimized
3.3 V PWM optimized
S18-0299-Rev. A, 19-Mar-18
Document Number: 76582
2
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
V
IN
DSBL#
THWn
P
GND
V
DRV
SW
SW
P
GND
SW
12 13 14 15
P
GND
P
GND
P
GND
GL
32
C
GND
2 ZCD_EN#
3 V
CIN
4 C
GND
5 BOOT
6 N.C.
34
V
IN
7 PHASE
8 V
IN
15 14 13 12
11 10
9
SiC638
www.vishay.com
PART MARKING INFORMATION
=
Pin 1 Indicator
Part Number Code
Siliconix Logo
ESD Symbol
Assembly Factory Code
Year Code
Week Code
Lot Code
Vishay Siliconix
P/N
LL
FYWW
P/N
=
=
=
F
Y
WW
LL
=
=
=
=
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
Input voltage
Control logic supply voltage
Drive supply voltage
Switch node (DC voltage)
Switch node (AC voltage)
(1)
BOOT voltage (DC voltage)
BOOT voltage (AC voltage)
(2)
BOOT to PHASE (DC voltage)
BOOT to PHASE (AC
voltage)
(3)
All logic inputs and outputs
(PWM, DSBL#, and THWn)
Max. operating junction temperature
Ambient temperature
Storage temperature
Electrostatic discharge protection
T
J
T
A
T
stg
Human body model, JESD22-A114
Charged device model, JESD22-C101
CONDITIONS
V
IN
V
CIN
V
DRV
V
SWH
V
BOOT
V
BOOT-PHASE
LIMIT
-0.3 to +30
-0.3 to +7
-0.3 to +7
-0.3 to +30
-7 to +35
35
40
-0.3 to +7
-0.3 to +8
-0.3 to V
CIN
+ 0.3
150
-40 to +125
-65 to +150
3000
1000
V
°C
V
UNIT
Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
(1)
The specification values indicated “AC” is V
SWH
to P
GND
-8 V (< 20 ns, 10 μJ), min. and 35 V (< 50 ns), max.
(2)
The specification value indicates “AC voltage” is V
BOOT
to P
GND
, 40 V (< 50 ns) max.
(3)
The specification value indicates “AC voltage” is V
BOOT
to V
PHASE
, 8 V (< 20 ns) max.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
Input voltage (V
IN
)
Drive supply voltage (V
DRV
)
Control logic supply voltage (V
CIN
)
BOOT to PHASE (V
BOOT-PHASE
, DC voltage)
Thermal resistance from junction to ambient
Thermal resistance from junction to case
MINIMUM
2.7
4.5
4.5
4
-
-
TYPICAL
-
5
5
4.5
10.6
1.6
MAXIMUM
24
5.5
5.5
5.5
-
-
°C/W
V
UNIT
S18-0299-Rev. A, 19-Mar-18
Document Number: 76582
3
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC638
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, V
IN
= 12 V, V
DRV
and V
CIN
= 5 V, T
A
= 25 °C)
PARAMETER
POWER SUPPLY
V
DSBL#
= 0 V, no switching, V
PWM
= FLOAT
Control logic supply current
I
VCIN
V
DSBL#
= 5 V, no switching, V
PWM
= FLOAT
V
DSBL#
= 5 V, f
S
= 300 kHz, D = 0.1
f
S
= 300 kHz, D = 0.1
Drive supply current
I
VDRV
f
S
= 1 MHz, D = 0.1
V
DSBL#
= 0 V, no switching
V
DSBL#
= 5 V, no switching
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage
PWM CONTROL INPUT (SiC638)
Rising threshold
Falling threshold
Tri-state voltage
Tri-state window
Tri-state rising threshold hysteresis
Tri-state falling threshold hysteresis
V
TH_PWM_R
V
TH_PWM_F
V
TRI_FLOAT
V
TRI_WINDOW
V
HYS_TRI_R
V
HYS_TRI_F
V
PWM
= 5 V, DSBL# = high
PWM input current
I
PWM
V
PWM
= 5 V, DSBL# = low
V
PWM
= 0 V, DSBL# = high
V
PWM
= 0 V, DSBL# = low
PWM CONTROL INPUT (SiC638A)
Rising threshold
Falling threshold
Tri-state Voltage
Tri-state window
Tri-state rising threshold hysteresis
Tri-state falling threshold hysteresis
V
TH_PWM_R
V
TH_PWM_F
V
TRI_FLOT
V
TRI_WINDOW
V
HYS_TRI_R
V
HYS_TRI_F
V
PWM
= 3.3 V, DSBL# = high
PWM input current
I
PWM
V
PWM
= 3.3 V, DSBL# = low
V
PWM
= 0 V, DSBL# = high
V
PWM
= 0 V, DSBL# = low
TIMING SPECIFICATIONS
Tri-state to GH/GL rising
propagation delay
Tri-state hold-off time
GH - turn off propagation delay
GH - turn on propagation delay
(dead time rising)
GL - turn off propagation delay
GL - turn on propagation delay
(dead time falling)
DSBL# Lo to GH/GL falling
propagation delay
PWM minimum on-time
t
PD_TRI_R
t
TSHO
t
PD_OFF_GH
t
PD_ON_GH
t
PD_OFF_GL
t
PD_ON_GL
t
PD_DSBL#_F
t
PWM_ON_MIN
Fig. 5
No load, see fig. 4
-
-
-
-
-
-
-
30
30
130
15
10
13
10
15
-
-
-
-
-
-
-
-
-
ns
V
PWM
= FLOAT
-
0.72
-
1.38
-
-
-
-
-
-
-
-
1.8
-
250
300
-
-
-
-
2.7
-
-
1.95
-
-
225
1
-225
-1
μA
mV
V
V
PWM
= FLOAT
-
0.72
-
1.38
-
-
-
-
-
-
-
-
2.3
-
225
325
-
-
-
-
4.2
-
-
3
-
-
350
1
-350
-1
μA
mV
V
V
F
I
F
= 2 mA
0.4
V
-
-
-
-
-
-
-
5
300
350
9
30
15
55
-
-
-
14
-
-
-
mA
μA
μA
SYMBOL
TEST CONDITION
LIMITS
MIN.
TYP.
MAX.
UNIT
S18-0299-Rev. A, 19-Mar-18
Document Number: 76582
4
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiC638
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, V
IN
= 12 V, V
DRV
and V
CIN
= 5 V, T
A
= 25 °C)
PARAMETER
DSBL# ZCD_EN# INPUT
DSBL# logic input voltage
ZCD_EN# logic input voltage
PROTECTION
Under voltage lockout
Under voltage lockout hysteresis
THWn flag set
(2)
THWn flag clear
(2)
THWn flag hysteresis
(2)
THWn output low
V
UVLO
V
UVLO_HYST
T
THWn_SET
T
THWn_CLEAR
T
THWn_HYST
V
OL_THWn
V
CIN
rising, on threshold
V
CIN
falling, off threshold
-
2.7
-
-
-
-
-
3.7
3.1
575
160
135
25
0.02
4.1
-
-
-
-
-
-
V
mV
°C
V
V
IH_DSBL#
V
IL_DSBL#
V
IH_ZCD_EN#
V
IL_ZCD_EN#
Input logic high
Input logic low
Input logic high
Input logic low
2
-
2
-
-
-
-
-
-
0.8
-
0.8
SYMBOL
TEST CONDITION
LIMITS
MIN.
TYP.
MAX.
UNIT
V
I
THWn
= 2 mA
Notes
(1)
Typical limits are established by characterization and are not production tested
(2)
Guaranteed by design
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
V
PWM_TH_R
the low side is turned OFF and the high side is
turned ON. When PWM input is driven below V
PWM_TH_F
the
high side is turned OFF and the low side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC638 and
SiC638A to pull the PWM input into the tri-state region (see
definition of PWM logic and Tri-State, fig. 4). If the PWM
input stays in this region for the Tri-state Hold-Off Period,
tTSHO, both high side and low side MOSFETs are turned
OFF. The function allows the VR phase to be disabled
without negative output voltage swing caused by inductor
ringing and saves a Schottky diode clamp. The PWM and
tri-state regions are separated by hysteresis to prevent false
triggering. The SiC638A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC638 thresholds are compatible with 5 V logic.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high side and low side MOSFETs. In this state,
standby current is minimized. If DSBL# is left unconnected,
an internal pull-down resistor will pull the pin to C
GND
and
shut down the IC.
S18-0299-Rev. A, 19-Mar-18
Document Number: 76582
5
For technical questions, contact:
powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Diode Emulation Mode (ZCD_EN#)
When ZCD_EN# pin is driven below V
IL_ZCD_EN#
. diode
emulation mode is enabled. If the PWM signal switches
below V
TH_PWM_F
then the LS MOSFET is under control of
the ZCD (zero crossing detect) comparator. If, after the
internal blanking delay, the inductor current becomes less
than or = 0 the low side is turned OFF. Light load efficiency
is improved by avoiding discharge of output capacitors. If
both high side and low side MOSFETs are required to be
turned OFF, regardless of inductor current, the PWM input
should be tri-stated.
Thermal Shutdown Warning (THWn)
The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect with a
maximum of 20 k, to V
CIN
. An internal temperature sensor
detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC638 and SiC638A do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.
Voltage Input (V
IN
)
This is the power input to the drain of the high side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
Linux开发
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
