CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Exceeding this voltage rating will not damage the device unless the peak input signal current (1mA) is also exceeded.
2.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
INPUT PARAMETERS
Input Offset Voltage
T
A
= 25
o
C for Equipment Design. Single Supply V+ = 30V, Dual Supply V
SUPPLY
=
±15V,
I
ABC
= 100µA Unless
Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
IO
T
A
= 25
o
C
T
A
= 0
o
C to 70
o
C
-
-
-
-
-
-
-
8
70
0.4
-
1
0.02
-
0.2
-
10
110
28.8
0.5
13.8
-14.5
30
4
0.4
1.4
0.68
4
15
18
1.8
1.0
2.6
5.0
7.0
8.0
0.2
0.3
0.50
0.70
12
-
-
-
-
-
-
-
-
-
-
-
150
-
-
-
-
mV
mV
mV
µA
µA
µA
µA
mW
dB
V
V
V
V
MHz
kHz
%
%
V
µV/
o
C
µV/V
nV/
H z
pA/
Hz
MΩ
pF
Input Offset Voltage Change
Input Offset Current
|∆V
IO
|
I
IO
Change in V
IO
between I
ABC
= 100µA
and I
ABC
= 5µA
T
A
= 25
o
C
T
A
= 0
o
C to 70
o
C
T
A
= 25
o
C
T
A
= 0
o
C to 70
o
C
Input Bias Current
I
I
Device Dissipation
Common Mode Rejection Ratio
Common Mode Input Voltage Range
P
D
CMRR
V
ICR
I
OUT
= 0mA
V+ = 30V (High)
V- = 0V (Low)
V+ = 15V
V- = -15V
27
1.0
12
-14
-
-
-
-
-
-
-
Unity Gain Bandwidth
Open Loop Bandwidth at -3dB Point
Total Harmonic Distortion
(Class A Operation)
Amplifier Bias Voltage
(Terminal 5 to Terminal 4)
Input Offset Voltage Temperature
Coefficient
Power Supply Rejection
1/F Noise Voltage
1/F Noise Current
Differential Input Resistance
Differential Input Capacitance
f
T
BW
OL
THD
I
C
= 7.5mA, V
CE
= 15V, I
ABC
= 500µA
I
C
= 7.5mA, V
CE
= 15V, I
ABC
= 500µA
P
D
= 220mW
P
D
= 600mW
V
ABC
∆V
IO
/∆T
∆V
IO
/∆V
E
N
I
N
R
I
C
I
f = 10Hz, I
ABC
= 50µA
f = 10Hz, I
ABC
= 50µA
I
ABC
= 20µA
f = 1MHz, V+ = 30V
-
-
0.50
-
3-2
CA3094, CA3094A, CA3094B
Electrical Specifications
PARAMETER
T
A
= 25
o
C for Equipment Design. Single Supply V+ = 30V, Dual Supply V
SUPPLY
=
±15V,
I
ABC
= 100µA Unless
Otherwise Specified
(Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUT PARAMETERS
(Differential Input Voltage = 1V)
Peak Output Voltage
(Terminal 6)
Peak Output Voltage
(Terminal 6)
Peak Output Voltage
(Terminal 8)
Peak Output Voltage
(Terminal 8)
With Q
13
“ON”
With Q
13
“OFF”
Positive
Negative
With Q
13
“OFF”
With Q
13
“ON”
Positive
Negative
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
OM
+
V
OM
-
V
CE(
SAT
)
V+ = 15V, V- = -15V,
R
L
= 2kΩ to 15V
V+ = 30V, I
C
= 50mA, Terminal 6
Grounded
V+ = 30V
hFE
C
O
V+ = 30V, V
CE
= 5V, I
C
= 50mA
f = 1MHz, All Remaining Terminals Tied
to Terminal 4
V+ = 30V, R
L
= 2kΩ to 30V
V+ = 15V, V- = -15V, R
L
= 2kΩ to -15V
V+ = 30V, R
L
= 2kΩ to GND
26
-
11
-
29.95
-
14.95
-
-
-
16,000
-
-
27
0.01
12
-14.99
29.99
0.040
14.99
-14.96
0.17
2
100,000
5.5
17
-
0.05
-
-14.95
-
-
-
-
0.80
10
-
-
-
pF
pF
V
V
V
V
V
V
V
V
V
µA
Collector-to-Emitter Saturation Voltage
(Terminal 8)
Output Leakage Current
(Terminal 6 to Terminal 4)
Composite Small Signal Current Transfer
Ratio (Beta) (Q
12
and Q
13
)
Output Capacitance
Terminal 6
Terminal 8
TRANSFER PARAMETERS
Voltage Gain
A
V+ = 30V, I
ABC
= 100µA,
∆V
OUT
= 20V,
R
L
= 2kΩ
20,000
86
1650
100,000
100
2200
500
50
0.70
-
-
2750
-
-
-
V/V
dB
µS
V/µs
V/µs
V/µs
Forward Transconductance to
Terminal 1
Slew Rate (Open
Loop)
Positive Slope
Negative Slope
gM
SR
I
ABC
= 500µA, R
L
= 2kΩ
-
-
Unity Gain (Non-Inverting Compensated)
I
ABC
= 500µA, R
L
= 2kΩ
-
Schematic Diagram
EXTERNAL FREQUENCY
COMPENSATION OR INHIBIT INPUT
D
3
Q
4
Q
6
D
2
Q
5
Q
9
DIFFERENTIAL
VOLTAGE 2
INPUT
DIFFERENTIAL
VOLTAGE
INPUT
AMPLIFIER
BIAS INPUT 5
I
ABC
8
Q
1
Q
2
Q
12
3
Q
11
Q
10
R
2
47kΩ
D
6
6
“SOURCE”
(DRIVE)
OUTPUT
“SINK”
OUTPUT
Q
13
Q
7
D
4
Q
8
D
5
R
1
2kΩ
1
7
V+
INPUTS
OUTPUT
MODE
“Source”
“Sink”
OUTPUT
TERM
6
8
INV
2
3
NON-
INV
3
2
Q
3
D
1
4
V-
3-3
CA3094, CA3094A, CA3094B
Operating Considerations
The “Sink” Output (Terminal 8) and the “Drive” Output
(Terminal 6) of the CA3094 are not inherently current (or
power) limited. Therefore, if a load is connected between
Terminal 6 and Terminal 4 (V- or Ground), it is important to
connect a current limiting resistor between Terminal 8 and
Terminal 7 (V+) to protect transistor Q13 under shorted load
conditions. Similarly, if a load is connected between
Terminal 8 and Terminal 7 (V+), the current limiting resistor
should be connected between Terminal 6 and Terminal 4 or
ground. In circuit applications where the emitter of the output
transistor is not connected to the most negative potential in
the system, it is recommended that a 100Ω current limiting
resistor be inserted between Terminal 7 and the V+ supply.
1/F Noise Measurement Circuit
When using the CA3094, A, or B audio amplifier circuits, it is
frequently necessary to consider the noise performance of the
device. Noise measurements are made in the circuit shown in
Figure 20. This circuit is a 30dB, non-inverting amplifier with
emitter follower output and phase compensation from
Terminal 2 to ground. Source resistors (R
S
) are set to 0Ω or
1MΩ for E noise and I noise measurements, respectively.
These measurements are made at frequencies of 10Hz,
100Hz and 1kHz with a 1Hz measurement bandwidth. Typical
values for 1/f noise at 10Hz and 50µA I
ABC
are:
E
N
=
18nV
⁄
Hz
and
I
N
=
1.8pA
⁄
Hz
.
Test Circuits
30V
NOTES:
7
5
2
CA3094
3
100Ω
4
100Ω
8
300kΩ
9.9kΩ
E
OUT
-
3. Input Offset Voltage: VIO
= ----------------
.
100
4. For Power Supply Rejection Test: (1) vary V+ by -2V; then (2)
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