November 2002
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FOR A our Technic ww.intersil.c
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contac TERSIL or w
IN
1-888-
®
CA3306, CA3306A,
CA3306C
6-Bit, 15 MSPS,
Flash A/D Converters
Features
•
•
•
•
•
•
CMOS Low Power with Video Speed (Typ) . . . . . 70mW
Parallel Conversion Technique
Signal Power Supply Voltage . . . . . . . . . . . 3V to 7.5V
15MHz Sampling Rate with Single 5V Supply
6-Bit Latched Three-State Output with Overflow Bit
Pin-for-Pin Retrofit for the CA3300
Description
The CA3306 family are CMOS parallel (FLASH) analog-to-digital
converters designed for applications demanding both low power
consumption and high speed digitization. Digitizing at 15MHz, for
example, requires only about 50mW.
The CA3306 family operates over a wide, full scale signal input volt-
age range of 1V up to the supply voltage. Power consumption is as
low as 15mW, depending upon the clock frequency selected. The
CA3306 types may be directly retrofitted into CA3300 sockets, offer-
ing improved linearity at a lower reference voltage and high operat-
ing speed with a 5V supply.
The intrinsic high conversion rate makes the CA3306 types ideally
suited for digitizing high speed signals. The overflow bit makes pos-
sible the connection of two or more CA3306s in series to increase
the resolution of the conversion system. A series connection of two
CA3306s may be used to produce a 7-bit high speed converter.
Operation of two CA3306s in parallel doubles the conversion speed
(i.e., increases the sampling rate from 15MHz to 30MHz).
Sixty-four paralleled auto balanced comparators measure the input
voltage with respect to a known reference to produce the parallel bit
outputs in the CA3306. Sixty-three comparators are required to
quantize all input voltage levels in this 6-bit converter, and the addi-
tional comparator is required for the overflow bit.
Applications
•
•
•
•
•
•
•
•
•
•
TV Video Digitizing
Ultrasound Signature Analysis
Transient Signal Analysis
High Energy Physics Research
High Speed Oscilloscope Storage/Display
General Purpose Hybrid ADCs
Optical Character Recognition
Radar Pulse Analysis
Motion Signature Analysis
Robot Vision
Part Number Information
PART NUMBER LINEARITY (INL, DNL)
CA3306E
CA3306CE
CA3306M
CA3306CM
CA3306D
CA3306CD
CA3306J3
CA3306J3
±0.5
LSB
±0.5
LSB
±0.5
LSB
±0.5
LSB
±0.5
LSB
±0.5
LSB
±0.5
LSB
±0.5
LSB
SAMPLING RATE
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
15MHz (67ns)
10MHz (100ns)
TEMP. RANGE (
o
C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
18 Ld PDIP
18 Ld PDIP
20 Ld SOIC
20 Ld SOIC
18 Ld SBDIP
18 Ld SBDIP
20 Ld CLCC
20 Ld CLCC
PKG. NO.
E18.3
E18.3
M20.3
M20.3
D18.3
D18.3
J20.B
J20.B
Pinouts
CA3306 (PDIP, SBDIP)
TOP VIEW
CA3306 (SOIC)
TOP VIEW
(MSB) B6 1
OVERFLOW 2
V
SS
3
NC 4
V
Z
5
CE2 6
CE1 7
CLK 8
PHASE 9
V
REF
+ 10
20 B5
19 B4
18 REF
CENTER
17 B3
16 B2
15 B1 (LSB)
14 V
DD
13 NC
12 V
IN
11 V
REF
-
CA3306 (CLCC)
TOP VIEW
OVER-
FLOW
B6
(MSB)
NC
3
V
SS
4
V
Z
5
NC 6
CE2 7
CE1 8
9 10 11 12 13
V
REF
+
V
REF
-
CLK
PHASE
V
IN
2
B5
OVERFLOW 2
V
SS
3
V
Z
4
CE2 5
CE2 6
CLK 7
PHASE 8
V
REF
+ 9
17 B4
REF
16
CENTER
15 B3
14 B2
13 B1 (LSB)
12 V
DD
11 V
IN
10 V
REF
-
1 20 19
18 REF
CENTER
17 B3
16 B2
15 B1 (LSB)
14 V
DD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
B4
(MSB) B6 1
18 B5
FN3102.2
1
CA3306, CA3306A, CA3306C
Functional Block Diagram
V
IN
φ
1
R/2
V
REF
+
R
φ
1
φ
2
φ
1
φ
2
COMP
64
D Q
CL
THREE-STATE
OVERFLOW
R
COMP
63
D Q
CL
B6 (MSB)
R
≅
120Ω
REF
CENTER
R
COMP
32
D Q
CL
COMPARATOR
LATCHES
AND
ENCODER
LOGIC
B5
D Q
CL
B4
R
COMP
2
R
V
REF
-
R/2
COMP
1
D Q
CL
B3
D Q
CL
B2
D Q
CL
B1 (LSB)
≅
50kΩ
CLOCK
CE1
φ
2 (SAMPLE UNKNOWN)
PHASE
φ
1 (AUTO BALANCE)
CE2
ZENER
6.2V NOMINAL
DIODE
V
SS
V
DD
V
SS
Typical Application Circuit
OF
1
2
6.2V
560Ω
+12V
+5V
5
6
CLOCK
+12V
5kΩ
+
CA741CE
7
8
9
0.1µF
CLK
PH
V
REF+
V
DD
12
0.2µF
V
IN
11
V
REF-
10
SIGNAL
INPUT
10µF
CE2
CE1
B2 14
B1 13
+5V
4
V
Z
B3 15
3
B6
OF
V
SS
CA3306
B5 18
B4 17
0.1µF
RC 16
B6
B5
B4
B3
B2
B1
(LSB)
DATA
OUTPUT
-
2
CA3306, CA3306A, CA3306C
Absolute Maximum Ratings
DC Supply Voltage Range, V
DD
Voltage Referenced to V
SS
Terminal . . . . . . . . . . . -0.5V to +8.5V
Input Voltage Range
All Inputs Except Zener. . . . . . . . . . . . . . . . . -0.5V to V
DD
+ 0.5V
DC Input Current
CLK, PH, CE1, CE2, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . .
±20mA
Thermal Information
Thermal Resistance (Typical, Note 1)
θ
JA
(
o
C/W)
θ
JC
(
o
C/W)
SBDIP Package. . . . . . . . . . . . . . . . . . . .
75
24
PDIP Package . . . . . . . . . . . . . . . . . . . . .
95
N/A
SOIC Package. . . . . . . . . . . . . . . . . . . . .
115
N/A
CLCC Package . . . . . . . . . . . . . . . . . . . .
80
28
Maximum Junction Temperature
Hermetic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
o
C
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 8V
Temperature Range (T
A
)
Ceramic Package (D Suffix) . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Plastic Package (E or M Suffix) . . . . . . . . . . . . . . . -40
o
C to 85
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.8V, V
SS
= V
REF
- = GND, Clock = 15MHz Square Wave for CA3306
or CA3306A, 10MHz for CA3306C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
6
CA3306, CA3306C
CA3306A
-
-
-
-
-
-
-
-
-
-
-
±0.25
±0.2
±0.25
±0.2
±0.5
±0.25
±0.5
±0.25
+0.1
-0.1
-
±0.5
±0.25
±0.5
±0.25
±1
±0.5
±1
±0.5
-
-
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
mV/
o
C
mV/
o
C
Differential Linearity Error,
DNL
Offset Error (Unadjusted)
CA3306, CA3306C
CA3306A
CA3306, CA3306C (Note 1)
CA3306A
Gain Error (Unadjusted)
CA3306, CA3306C (Note 2)
CA3306A
Gain Temperature Coefficient
Offset Temperature Coefficient
DYNAMIC CHARACTERISTICS
(Input Signal Level 0.5dB Below Full Scale)
Maximum Conversion Speed
CA3306C
CA3306, CA3306A
Maximum Conversion Speed
CA3306C
CA3306, CA3306A
Allowable Input Bandwidth
-3dB Input Bandwidth
Signal to Noise Ratio, SNR
RMSSignal
=
--------------------------------
RMSNoise
Signal to Noise Ratio, SINAD
RMSSignal
=
-----------------------------------------------------------
-
RMSNoise+Distortion
Total Harmonic Distortion, THD
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 5MHz
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 5MHz
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 5MHz
Effective Number of Bits, ENOB
f
S
= 15MHz, f
IN
= 100kHz
f
S
= 15MHz, f
IN
= 5MHz
(Note 4)
φ
1,
φ
2
≥
Minimum
(Note 4)
10
15
12
18
DC
-
-
-
-
-
-
-
-
-
13
20
-
-
-
30
34.6
33.4
34.2
29.0
-46.0
-30.0
5.5
4.5
-
-
-
-
f
CLOCK/2
-
-
-
-
-
-
-
-
-
MSPS
MSPS
MSPS
MSPS
MHz
MHz
dB
dB
dB
dB
dBc
dBc
Bits
Bits
3
CA3306, CA3306A, CA3306C
Electrical Specifications
PARAMETER
ANALOG INPUTS
Positive Full Scale Input Range
Negative Full Scale Input Range
Input Capacitance
Input Current
INTERNAL VOLTAGE REFERENCE
Zener Voltage
Zener Dynamic Impedance
Zener Temperature Coefficient
REFERENCE INPUTS
Resistor Ladder Impedance
DIGITAL INPUTS
Maximum V
IN
, Logic 0
Maximum V
IN
, Logic 1
Digital Input Current
Digital Input Current
DIGITAL OUTPUTS
Digital Output Three-State Leakage
Digital Output Source Current
Digital Output Sink Current
TIMING CHARACTERISTICS
Auto Balance Time (
φ
1)
Sample Time (
φ
2)
CA3306C
CA3306, CA3306A
CA3306C
CA3306, CA3306A
Aperture Delay
Aperture Jitter
Output Data Valid Delay, t
D
CA3306C
CA3306, CA3306A
Output Data Hold Time, t
H
Output Enable Time, t
EN
Output Disable Time, t
DIS
POWER SUPPLY CHARACTERISTICS
I
DD
Current, Refer to Figure 4 CA3306C
CA3306, CA3306A
I
DD
Current
NOTES:
1. OFFSET ERROR is the difference between the input voltage that causes the 00 to 01 output code transition and (V
REF
+ - V
REF
-)/128.
2. GAIN ERROR is the difference the input voltage that causes the 3F
16
to overflow output code transition and (V
REF
+ - V
REF
-) x 127/128.
3. The total input voltage range, set by V
REF
+ and V
REF
-, may be in the range of 1 to (V
DD
+ 1) V.
4. Parameter not tested, but guaranteed by design or characterization.
Continuous
φ
1
Continuous Conversion (Note 4)
-
-
-
11
14
7.5
20
25
15
mA
mA
mA
(Note 4)
(Note 4)
50
33
33
22
-
-
-
-
15
-
-
-
-
-
-
8
100
35
30
25
20
15
V
OUT
= 0V, 5V
V
OUT
= 4.6V
V
OUT
= 0.4V
-
-1.6
3.2
±1
-
-
±5
-
-
µA
mA
mA
All Digital Inputs (Note 4)
All Digital Inputs (Note 4)
Except CLK, V
IN
= 0V, 5V
CLK Only
-
0.7 x
V
DD
-
-
-
-
±1
±100
0.3 x
V
DD
-
±5
±200
V
V
µA
µA
650
1100
1550
Ω
I
Z
= 10mA
I
Z
= 10mA, 20mA
5.4
-
-
6.2
12
-0.5
7.4
25
-
V
Ω
mV/
o
C
V
IN
= 4.92V, V
DD
= 5V
(Notes 3, 4)
(Notes 3, 4)
1
-0.5
-
-
4.8
0
15
-
V
DD
+
0.5
V
DD
- 1
-
±500
V
V
pF
µA
T
A
= 25
o
C, V
DD
= 5V, V
REF
+ = 4.8V, V
SS
= V
REF
- = GND, Clock = 15MHz Square Wave for CA3306
or CA3306A, 10MHz for CA3306C
(Continued)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
∞
∞
5000
5000
-
-
50
40
-
-
-
ns
ns
ns
ns
ps
P-P
ns
ns
ns
ns
ns
4
CA3306, CA3306A, CA3306C
Timing Waveforms
COMPARATOR DATA IS LATCHED
CLOCK IF
PHASE IS HIGH
DECODED DATA IS SHIFTED TO OUTPUT REGISTERS
φ
2
φ
1
φ
2
φ
1
φ
2
CLOCK IF
PHASE IS LOW
AUTO
BALANCE
SAMPLE
N+1
t
D
t
H
AUTO
BALANCE
SAMPLE
N+2
DATA
N-2
DATA
N-1
DATA
N
FIGURE 1. INPUT-TO-OUTPUT
CE1
CE2
t
DIS
t
EN
t
DIS
HIGH
IMPEDANCE
t
DIS
HIGH
IMPEDANCE
DATA
DATA
BITS 1-6
DATA
HIGH
IMPEDANCE
OF
DATA
DATA
FIGURE 2. OUTPUT ENABLE
5
单片机
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