CAT130xx
Voltage Supervisor with Microwire Serial
CMOS EEPROM
FEATURES
Precision Power Supply Voltage Monitor
5V, 3.3V, 3V & 2.5V systems
7 threshold voltage options
Active High or Low Reset
Valid reset guaranteed at V
CC
= 1 V
High Speed Operation
Selectable x8 or x16 memory organization
Low power CMOS technology
1,000,000 Program/Erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant 8-pin SOIC package
For Ordering Information details, see page 13.
DESCRIPTION
The CAT130xx (see table below) are memory and
supervisory solutions for microcontroller based
systems. A CMOS serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together. Memory interface is via
Microwire serial protocol.
The CAT130xx provides a precision V
CC
sense circuit
with two reset output options: CMOS active low output
or CMOS active high. The RESET output is active
whenever V
CC
is below the reset threshold or falls
below the reset threshold voltage.
The power supply monitor and reset circuit protect
system controllers during power up/down and against
brownout conditions. Seven reset threshold voltages
support 5V, 3.3V, 3V and 2.5V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 240ms after the supply
voltage exceeds the reset threshold level.
PIN CONFIGURATION
SOIC (W)
CS
SK
DI
DO
1
2
3
4
8 V
CC
¯¯¯¯
7 RST/ RST
6 ORG
5 GND
MEMORY SIZE SELECTOR
Product
13001
13004
13008
13016
Memory density
1-Kbit
4-Kbit
8-Kbit
16-Kbit
PIN FUNCTION
Pin Name
CS
SK
DI
DO
GND
ORG
¯¯¯¯
RST/ RST
V
CC
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Ground
Memory Organization
Reset Output
Power Supply
THRESHOLD SUFFIX SELECTOR
Nominal Threshold
Voltage
4.63V
4.38V
4.00V
3.08V
2.93V
2.63V
2.32V
Threshold Suffix
Designation
L
M
J
T
S
R
Z
Note:
When the ORG pin is connected to V
CC
, the x16 organization is
selected. When it is connected to ground, the x8 pin is selected. If
the ORG pin is left unconnected, then an internal pullup device will
select the x16 organization.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1121 Rev. A
CAT130xx
BLOCK DIAGRAM
V
CC
DO
ORG
CS
SK
DI
EEPROM
VOLTAGE
DETECTOR
RST or RST
V
SS
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground
RELIABILITY CHARACTERISTICS
(3)
Symbol
NEND
(4)
(2)
Ratings
-65 to +150
-0.5 to +6.5
Units
°C
V
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
TDR
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +5.5V unless otherwise specified.
Symbol
I
CC
I
SB
I
L
V
IL
V
IH
V
OL
V
OH
Parameter
Supply Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
2.4
-0.5
2.0
12
10
Min.
Limits
Typ.
Max.
3
25
20
2
0.8
V
CC
+ 0.5
0.4
V
CC
≥
2.5V, I
OL
= 2.1mA
V
CC
≥
4.5V, I
OH
= -0.4mA
Test Condition
Read or Write at 1MHz
V
CC
< 5.5V; All I/O Pins at V
SS
or V
CC
V
CC
< 3.6V; All I/O Pins at V
SS
or V
CC
Pin at GND or V
CC
Units
mA
μA
μA
V
V
V
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Block Mode, V
CC
= 5 V, 25°C
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
2
Doc. No. 1121 Rev. A
CAT130xx
A.C. CHARACTERISTICS (MEMORY)
(1)
V
CC
= +2.5V to 5.5V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
f
SK
t
CSS
t
CSH
t
CSMIN
t
SKHI
t
SKLOW
t
DIS
t
DIH
t
PD1
t
PD0
(1)
t
HZ
Parameter
Clock Frequency
CS Setup Time
CS Hold Time
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Status Valid
Program/Erase Pulse Width
Power-up to Ready Mode
Min
DC
50
0
0.25
0.25
0.25
100
100
Max
2000
Units
kHz
ns
ns
µs
µs
µs
ns
ns
0.25
0.25
100
0.25
5
1
µs
µs
ns
µs
ms
ms
t
SV
t
EW
t
PU
Notes:
(1)
(2)
(3)
(2), (3)
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Levels
Input Levels
Timing Reference Levels
Timing Reference Levels
Output Load
≤
50 ns
0.4V to 2.4V (4.5V < V
CC
< 5.5V)
0.2V
CC
to 0.7V
CC
(2.5V < V
CC
< 4.5V)
0.8V, 2.0V (4.5V < V
CC
< 5.5V)
0.5V
CC
(2.5V < V
CC
< 4.5V)
Current Source: I
OL max
/ I
OH max
; C
L
= 100pF
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1121 Rev. A
CAT130xx
ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
V
CC
= Full range, T
A
= -40ºC to +85ºC unless otherwise noted. Typical values at T
A
= +25ºC and V
CC
= 5V for
L/M/J versions, V
CC
= 3.3V for T/S versions, V
CC
= 3V for R version and V
CC
= 2.5V for Z version.
Symbol
V
TH
Parameter
Reset Threshold Voltage
Threshold
L
M
J
T
S
R
Z
Conditions
T
A
= +25ºC
T
A
= -40ºC to +85ºC
T
A
= +25ºC
T
A
= -40ºC to +85ºC
T
A
= +25ºC
T
A
= -40ºC to +85ºC
T
A
= +25ºC
T
A
= -40ºC to +85ºC
T
A
= +25ºC
T
A
= -40ºC to +85ºC
T
A
= +25ºC
T
A
= -40ºC to +85ºC
T
A
= +25ºC
T
A
= -40ºC to +85ºC
Min
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
Min
Typ
(1)
30
V
CC
= V
TH
to (V
TH
-100mV)
T
A
= -40ºC to +85ºC
V
CC
= V
TH
min, I
SINK
= 1.2 mA
R/S/T/Z
V
CC
= V
TH
min, I
SINK
= 3.2 mA
J/L/M
V
CC
> 1.0V, I
SINK
= 50µA
V
OH
¯¯¯¯¯¯
RESET Output Voltage High
(Push-pull, active LOW,
CAT130xx9)
RESET Output Voltage Low
V
OL
(Push-pull, active HIGH,
CAT130xx1)
RESET Output Voltage High
V
OH
Notes:
(1)
(2)
Production testing done at T
A
= +25ºC; limits over temperature guaranteed by design only.
¯¯¯¯¯¯
RESET output for the CAT130xx9; RESET output for the CAT130xx1.
Typ
4.63
4.38
4.00
3.08
2.93
2.63
2.32
Max
4.70
4.75
4.45
4.50
4.06
4.10
3.11
3.15
2.96
3.00
2.66
2.70
2.35
2.38
Max
Units
V
Symbol Parameter
Reset Threshold Tempco
t
RPD
t
PURST
V
CC
to Reset Delay
(2)
Reset Active Timeout Period
¯¯¯¯¯¯
RESET Output Voltage Low
(Push-pull, active LOW,
CAT130xx9)
Conditions
Units
ppm/ºC
µs
20
140
240
460
0.3
0.4
0.3
0.8V
CC
ms
V
OL
V
V
CC
= V
TH
max, I
SOURCE
= -500µA
R/S/T/Z
V
CC
= V
TH
max, I
SOURCE
= -800µA
J/L/M
V
CC
> V
TH
max, I
SINK
= 1.2mA
R/S/T/Z
V
CC
> V
TH
max, I
SINK
= 3.2mA
J/L/M
1.8V < V
CC
≤
V
TH
min,
I
SOURCE
= -150µA
V
V
CC
- 1.5
0.3
V
0.4
0.8V
CC
V
(Push-pull, active HIGH,
CAT130xx1)
Doc. No. 1121 Rev. A
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT130xx
PIN DESCRIPTION
¯¯¯¯¯¯
RESET/RESET:
The reset output is available in two
versions: CMOS Active Low (CAT130xx9) and CMOS
Active High (CAT130xx1). Both versions are push-pull
outputs for high efficiency.
DI:
The serial data input pin accepts op-codes,
addresses and data. The input data is latched on the
rising edge of the SK clock input.
DO:
The serial data output pin is used to transfer data
out of the device. The data is shifted out on the rising
edge of the SK clock.
SK:
The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT130xx device.
CS:
The chip select input pin is used to enable/disable
the CAT130xx. When CS is high, the device is
selected and accepts op-codes, addresses and data.
Upon receiving a Write or Erase instruction, the falling
edge of CS will start the internal write cycle to the
selected memory location.
ORG:
The memory organization input selects the memory
configuration as either register of 16 bits (ORG tied to
V
CC
or floating) or 8 bits (ORG connected to GND).
RESET CONTROLLER DESCRIPTION
The reset signal is asserted LOW for the CAT130xx9
and HIGH for the CAT130xx1 when the power supply
voltage falls below the threshold trip voltage
and remains asserted for at least 140ms (t
PURST
) after
the power supply voltage has risen above the
threshold. Reset output timing is shown in Figure 1.
The CAT130xx devices protect
μPs
against brownout
failure. Short duration V
CC
transients of 4μsec or less and
100mV amplitude typically do not generate a Reset pulse.
Figure 2 shows the maximum pulse duration of
negative-going V
CC
transients that do not cause a
reset condition. As the amplitude of the transient goes
further below the threshold (increasing V
TH
- V
CC
), the
maximum pulse duration decreases. In this test, the
V
CC
starts from an initial voltage of 0.5V above the
threshold and drops below it by the amplitude of the
overdrive voltage (V
TH
- V
CC
).
TRANSIENT DURATION [µs]
T
AMB
= 25ºC
CAT130xxZ
DEVICE OPERATION
The CAT130xx products combine the accurate
voltage monitoring capabilities of a standalone voltage
supervisor with the high quality and reliability of
standard EEPROMs from Catalyst Semiconductor.
CAT130xxM
RESET OVERDRIVE V
TH
- V
CC
[mV]
Figure 2. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
V
CC
V
TH
V
RVALID
t
PURST
t
RPD
t
PURST
t
RPD
RESE T
CAT130xx9
RESE T
CAT130xx1
Figure 1. RESET Output Timing
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1121 Rev. A
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