CAT15002, CAT15004
Voltage Supervisor with 2-Kb and 4-Kb SPI
Serial CMOS EEPROM
FEATURES
Precision Power Supply Voltage Monitor
5V, 3.3V, 3V & 2.5V systems
7 threshold voltage options
Active High or Low Reset
Valid reset guaranteed at V
CC
= 1V
10MHz SPI compatible
16-byte page write buffer
Low power CMOS technology
1,000,000 Program/Erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant 8-pin SOIC package
For Ordering Information details, see page 14.
DESCRIPTION
The CAT15002/04 (see table below) are memory and
supervisory solutions for microcontroller based
systems. A CMOS serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together. Memory interface is via SPI
bus serial interface.
The CAT15002/04 provides a precision V
CC
sense
circuit with two reset output options: CMOS active low
output or CMOS active high. The RESET output is
active whenever V
CC
is below the reset threshold or
falls below the reset threshold voltage.
The power supply monitor and reset circuit protect
system controllers during power up/down and against
brownout conditions. Seven reset threshold voltages
support 5V, 3.3V, 3V and 2.5V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 240ms after the supply
voltage exceeds the reset threshold level.
PIN CONFIGURATION
SOIC (W)
¯¯
CS
SO
¯¯¯
WP
V
SS
1
2
3
4
8 V
CC
7 RST/¯¯¯¯
RST
6 SCK
5 SI
MEMORY SIZE SELECTOR
Product
15002
15004
Memory density
2-Kbit
4-Kbit
PIN FUNCTION
Pin Name
¯¯
CS
SO
¯¯¯
WP
V
SS
SI
SCK
¯¯¯¯
RST/RST
V
CC
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock Input
Reset Output
Power Supply
THRESHOLD SUFFIX SELECTOR
Nominal Threshold
Voltage
4.63V
4.38V
4.00V
3.08V
2.93V
2.63V
2.32V
Threshold Suffix
Designation
L
M
J
T
S
R
Z
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1126 Rev. A
CAT15002, CAT15004
BLOCK DIAGRAM
V
CC
SO
SCK
SI
CS
WP
EEPROM
VOLTAGE
DETECTOR
RST or RST
V
SS
ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
(1)
Ratings
-65 to +150
(2)
Units
°C
V
Voltage on Any Pin with Respect to Ground
RELIABILITY CHARACTERISTICS
(3)
Symbol
NEND
(4)
TDR
Parameter
Endurance
Data Retention
-0.5 to +6.5
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +5.5V unless otherwise specified.
Symbol Parameter
I
CC
I
SB
I
L
V
IL
V
IH
V
OL
V
OH
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+ 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than V
CC
+ 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5V, 25°C
Min.
Limits
Typ.
12
10
Max.
2
25
20
2
0.3 V
CC
V
CC
+ 0.5
0.4
Test Condition
Read or Write at 10MHz, SO open
¯¯
V
CC
< 5.5V; V
IN
= V
SS
or V
CC
, CS = V
CC
¯¯
V
CC
< 3.6V; V
IN
= V
SS
or V
CC
, CS = V
CC
Pin at GND or V
CC
Units
mA
μA
μA
V
V
Supply Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
CC
- 0.8
-0.5
0.7 V
CC
V
CC
≥
2.5V, I
OL
= 3.0mA
V
CC
≥
2.5V, I
OH
= -1.6mA
V
V
Doc. No. 1126 Rev. A
2
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT15002, CAT15004
A.C. CHARACTERISTICS (MEMORY)
(1)
V
CC
= 2.5V to 5.5V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI(2)
t
FI(2)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
t
WC(4)
t
PU(2) (3)
Notes
:
(1)
(2)
(3)
(4)
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
¯¯
t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Parameter
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
¯¯¯¯¯
HOLD to Output Low Z
Input Rise Time
Input Fall Time
¯¯¯¯¯ Setup Time
HOLD
¯¯¯¯¯
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
¯¯¯¯¯
HOLD to Output High Z
¯¯
CS High Time
¯¯
CS Setup Time
¯¯
CS Hold Time
¯¯¯ Setup Time
WP
¯¯¯ Hold Time
WP
Write Cycle Time
Power-up to Ready Mode
Min.
DC
20
20
40
40
Max.
10
Units
MHz
ns
ns
ns
ns
25
2
2
0
10
40
0
20
25
15
15
15
10
10
5
1
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Levels
Timing Reference Levels
Output Load
≤
10ns
0.3 V
CC
to 0.7 V
CC
0.5 V
CC
Current Source: I
OL
max/ I
OH
max; C
L
= 50pF
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1126 Rev. A
CAT15002, CAT15004
ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
V
CC
= Full range, T
A
= -40°C to +85°C unless otherwise noted. Typical values at T
A
= +25°C and V
CC
= 5V for
L/M/J versions, V
CC
= 3.3V for T/S versions, V
CC
= 3V for R version and V
CC
= 2.5V for Z version.
Symbol
V
TH
Parameter
Reset Threshold Voltage
Threshold
L
M
J
T
S
R
Z
Conditions
T
A
= +25°C
T
A
= -40°C to +85°C
T
A
= +25°C
T
A
= -40°C to +85°C
T
A
= +25°C
T
A
= -40°C to +85°C
T
A
= +25°C
T
A
= -40°C to +85°C
T
A
= +25°C
T
A
= -40°C to +85°C
T
A
= +25°C
T
A
= -40°C to +85°C
T
A
= +25°C
T
A
= -40°C to +85°C
Min
4.56
4.50
4.31
4.25
3.93
3.89
3.04
3.00
2.89
2.85
2.59
2.55
2.28
2.25
Min
Typ
(1)
30
V
CC
= V
TH
to (V
TH
-100mV)
T
A
= -40°C to +85°C
V
CC
= V
TH
min, I
SINK
= 1.2mA
R/S/T/Z
V
CC
= V
TH
min, I
SINK
= 3.2mA
J/L/M
V
CC
> 1.0V, I
SINK
= 50µA
¯¯¯¯¯¯
RESET Output Voltage High
(Push-pull, active LOW,
CAT150xx9)
RESET Output Voltage Low
V
OL
(Push-pull, active HIGH,
CAT150xx1)
RESET Output Voltage High
V
OH
Notes:
(1)
(2)
Production testing done at T
A
= +25ºC; limits over temperature guaranteed by design only.
RESET output for the CAT150xx9; RESET output for the CAT150xx1.
Typ
4.63
4.38
4.00
3.08
2.93
2.63
2.32
Max
4.70
4.75
4.45
4.50
4.06
4.10
3.11
3.15
2.96
3.00
2.66
2.70
2.35
2.38
Max
Units
V
Symbol Parameter
Reset Threshold Tempco
t
RPD
t
PURST
V
CC
to Reset Delay
(2)
Reset Active Timeout Period
Conditions
Units
ppm/°C
µs
20
140
240
460
0.3
0.4
0.3
0.8V
CC
ms
V
OL
¯¯¯¯¯¯
RESET Output Voltage Low
(Push-pull, active LOW,
CAT150xx9)
V
V
OH
V
CC
= V
TH
max, I
SOURCE
= -500µA
R/S/T/Z
V
CC
= V
TH
max, I
SOURCE
= -800µA
J/L/M
V
CC
> V
TH
max, I
SINK
= 1.2mA
R/S/T/Z
V
CC
> V
TH
max, I
SINK
= 3.2mA
J/L/M
1.8V < V
CC
≤
V
TH
min,
I
SOURCE
= -150µA
V
V
CC
- 1.5
0.3
V
0.4
0.8V
CC
V
(Push-pull, active HIGH,
CAT150xx1)
Doc. No. 1126 Rev. A
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT15002, CAT15004
PIN DESCRIPTION
¯¯¯¯¯¯
RESET/RESET:
Reset output is available in two
versions: CMOS Active Low (CAT150xx9) and CMOS
Active High (CAT150xx1). Both versions are push-pull
outputs for high efficiency.
SI:
The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
SO:
The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT15002/04.
¯¯
CS:
The chip select input pin is used to enable/disable
¯¯
the CAT15002/04. When CS is high, the SO output is
tri-stated (high impedance) and the device is in
Standby Mode (unless an internal write operation is in
progress).
Every communication session between host
and CAT15002/04 must be preceded by a high to low
transition and concluded with a low to high transition of
¯¯
the CS input.
¯¯¯:
The write protect input pin will allow all write
WP
operations to the device when held high. When ¯¯¯
WP
pin is tied low all write operations are inhibited.
DEVICE OPERATION
The CAT15002/04 products combine the accurate
voltage monitoring capabilities of a standalone voltage
supervisor with the high quality and reliability of
standard EEPROMs from Catalyst Semiconductor.
RESET CONTROLLER DESCRIPTION
The reset signal is asserted LOW for the CAT150xx9
and HIGH for the CAT150xx1 when the power supply
voltage falls below the threshold trip voltage and
remains asserted for at least 140ms (t
PURST
) after the
power supply voltage has risen above the threshold.
Reset output timing is shown in Figure 1.
The CAT15002/04 devices protect µPs against brown-out
failure. Short duration V
CC
transients of 4µsec or less and
100mV amplitude typically do not generate a Reset pulse.
V
CC
V
TH
V
RVALID
t
PURST
t
RPD
t
PURST
t
RPD
RESE T
CAT150xx9
RESE T
CAT150xx1
Figure 1. RESET Output Timing
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1126 Rev. A
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