CAT24C03/05
FEATURES
2-Kb and 4-Kb I
2
C Serial EEPROM with Partial Array Write Protection
DEVICE DESCRIPTION
The CAT24C03/CAT24C05 is a 2-kb/4-kb CMOS Serial
EEPROM device organized internally as 16/32 pages
of 16 bytes each, for a total of 256x8/512x8 bits. These
devices support both Standard (100kHz) as well as Fast
(400kHz) I
2
C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
Write operations can be inhibited for upper half of memory
by taking the WP pin High.
External address pins make it possible to address
up to eight CAT24C03 or four CAT24C05 devices on the
same bus.
■
Supports Standard and Fast I
2
C Protocol
■
1.8 V to 5.5 V Supply Voltage Range
■
16-Byte Page Write Buffer
■
Hardware Write Protection for upper half of
memory
■
Schmitt Triggers and Noise Suppression Filters
on I
2
C Bus Inputs (SCL and SDA).
■
Low power CMOS technology
■
1,000,000 program/erase cycles
■
100 year data retention
■
Industrial temperature range
■
RoHS-compliant 8-lead PDIP, SOIC, and TSSOP,
8-pad TDFN and 5-lead TSOT-23 packages.
For Ordering Information details, see page 17.
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TSSOP (Y)
TDFN (VP2)
CAT24C05 / 03
NC / A0
A1 / A1
A2 / A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SCL
VSS
SDA
1
2
3
4
VCC
5
WP
FUNCTIONAL SYMBOL
VCC
TSOT-23 (TD)
SCL
A2, A1, A0
WP
CAT24C03
CAT24C05
SDA
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
NC
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
* Catalyst carries the I
2
C protocol under a license from the Philips Corporation.
VSS
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1116, Rev. B
CAT24C03/05
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
-65°C to +150°C
-0.5 V to +6.5 V
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
-0.5
Min
Max
1
1
1
1
V
CC
x 0.3
Units
mA
mA
μA
μA
V
V
V
V
V
CC
x 0.7 V
CC
+ 0.5
0.4
0.2
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
C
IN(3)
C
IN(3)
I
WP(5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH,
V
CC
= 5.5 V
V
IN
< V
IH,
V
CC
= 3.3 V
V
IN
< V
IH,
V
CC
= 1.8 V
V
IN
> V
IH
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Max
8
6
200
150
100
1
Units
pF
pF
μA
Doc. No. 1116, Rev. B
2
CAT24C03/05
A.C. CHARACTERISTICS
(1)
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C.
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F(2)
t
SU:STO
t
BUF
t
AA
t
DH
T
i(2)
t
SU:WP
t
HD:WP
t
WR
t
PU(2, 3)
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Fast
Min
0.6
1.3
0.6
0.6
0
100
Max
400
Units
kHz
μs
μs
μs
μs
μs
ns
300
300
0.6
1.3
ns
ns
μs
μs
0.9
100
100
0
2.5
μs
ns
ns
μs
μs
5
1
ms
ms
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
Min
4
4.7
4
4.7
0
250
Max
100
1000
300
4
4.7
3.5
100
100
0
2.5
5
1
A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
≤
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3 mA (V
CC
≥
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1116, Rev. B
CAT24C03/05
POWER-ON RESET (POR)
The CAT24C03/05 incorporates Power-On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state.
The CAT24C03/05 device will power up into Standby mode
after V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
I
2
C BUS PROTOCOL
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. For normal Read/Write opera-
tions, the first 4 bits of the Slave address are fixed at
1010 (Ah). The next 3 bits are used as programmable
address bits when cascading multiple devices and/or as
internal address bits. The last bit of the slave address,
R/W, specifies whether a Read (1) or Write (0) opera-
tion is to be performed. The 3 address space extension
bits are assigned as illustrated in Figure 2. A
2
, A
1
and
A
0
must match the state of the external address pins,
and a
8
(CAT24C05) is internal address bit.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
th
clock cycle (Figure 3). The Slave will
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9
th
clock cycle. As long as the Master acknowledges
the data, the Slave will continue transmitting. The Master
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.
PIN DESCRIPTION
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2:
The Address inputs set the device ad-
dress when cascading multiple devices. When not driven,
these pins are pulled LOW internally.
WP:
The Write Protect input pin inhibits the write opera-
tions for upper half of memory, when pulled HIGH. When
not driven, this pin is pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24C03/05 supports the Inter-Integrated Circuit
(I
2
C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock and
all START and STOP conditions. The CAT24C03/05 acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver.
Doc. No. 1116, Rev. B
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
Figure 1. START/STOP Conditions
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1
1
0
0
1
1
0
0
A2
A2
A1
A1
A0
a8
R/W
R/W
CAT24C03
CAT24C05
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
ACK SETUP (≥ tSU:DAT)
Figure 4. Bus Timing
tF
tLOW
tHIGH
tLOW
tR
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1116, Rev. B
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