digital converters with an integrated precision reference.
They use a single 2.7V to 5.5V supply and communicate
through an I
2
C Interface. The LTC2461 is single-ended
with a 0V to 1.25V input range and the LTC2463 is dif-
ferential with a 1.25V input range. Both ADCs include a
1.25V integrated reference with 2ppm/°C drift perfor-
mance and 0.1% initial accuracy. The converters are
available in a 12-pin 3mm
×
3mm DFN package or an
MSOP-12 package. They include an integrated oscillator
and perform conversions with no latency for multiplexed
applications. The LTC2461/LTC2463 include a proprietary
input sampling scheme that reduces the average input
current several orders of magnitude when compared to
conventional delta sigma converters.
Following a single conversion, the LTC2461/LTC2463
automatically power down the converter and can also be
configured to power down the reference. When both the
ADC and reference are powered down, the supply current
is reduced to 200nA.
The LTC2461/LTC2463 can sample at 60 conversions per
second and, due to the very large oversampling ratio,
have extremely relaxed antialiasing requirements. Both
include continuous internal offset and fullscale calibration
algorithms which are transparent to the user, ensuring ac-
curacy over time and the operating temperature range.
V
REF
vs Temperature
2.7V TO 5.5V
0.1µF
0.1µF
REFOUT
IN
+
LTC2463
IN
–
0.1µF
REF
–
0.1µF
COMP V
CC
SCL
SDA
A0
GND
24613
TA01a
n
n
n
n
n
16-Bit Resolution, No Missing Codes
Internal Reference, High Accuracy 10ppm/°C (Max)
Single-Ended (LTC2461) or Differential (LTC2463)
2LSB Offset Error (Typ)
0.01% Gain Error (Typ)
60 Conversions Per Second
Single Conversion Settling Time for Multiplexed
Applications
1.5mA Supply Current
200nA Sleep Current
Internal Oscillator—No External Components
Required
2-Wire I
2
C Interface with Two Addresses Plus One
Global Address for Synchronization
Ultra-Tiny, 12-Lead, 3mm
×
3mm DFN and MSOP
Packages
APPLICATIONS
n
n
n
n
n
n
System Monitoring
Environmental Monitoring
Direct Temperature Measurements
Instrumentation
Data Acquisition
Embedded ADC Upgrades
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
TYPICAL APPLICATION
1.2520
REFERENCE OUTPUT VOLTAGE (V)
1.2515
1.2510
1.2505
1.2500
1.2495
1.2490
1.2485
1.2480
–50
0.1µF
10µF
10k
10k
I
2
C
INTERFACE
10k
R
–30
–10 10
30
50
TEMPERATURE (°C)
70
90
24613 TA01b
24613fa
1
LTC2461/LTC2463
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (V
CC
) ................................... –0.3V to 6V
Analog Input Voltage
(V
IN+
, V
IN –
, V
IN
, V
REF –
,
V
COMP
, V
REFOUT
) ...........................–0.3V to (V
CC
+ 0.3V)
Digital Voltage
(V
SDA
, V
SCL
, V
A0
) ..........................–0.3V to (V
CC
+ 0.3V)
Storage Temperature Range .................. –65°C to 150°C
Operating Temperature Range
LTC2461C/LTC2463C ............................... 0°C to 70°C
LTC2461I/LTC2463I .............................–40°C to 85°C
PIN CONFIGURATION
LTC2463
TOP VIEW
REFOUT
COMP
A0
GND
SCL
SDA
1
2
3
4
5
6
13
12 V
CC
11 GND
10 IN
–
9 IN
+
8 REF
–
7 GND
REFOUT
COMP
A0
GND
SCL
SDA
1
2
3
4
5
6
LTC2463
TOP VIEW
12
11
10
9
8
7
V
CC
GND
IN
–
IN
+
REF
–
GND
DD PACKAGE
12-LEAD (3mm
×
3mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 43°C/W
EXPOSED PAD (PIN 13)
LTC2461
TOP VIEW
REFOUT
COMP
A0
GND
SCL
SDA
1
2
3
4
5
6
13
12 V
CC
11 GND
10 GND
9 IN
8 REF
–
7 GND
LTC2461
MS PACKAGE
12-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 135°C/W
TOP VIEW
REFOUT
COMP
A0
GND
SCL
SDA
1
2
3
4
5
6
12
11
10
9
8
7
V
CC
GND
GND
IN
REF
–
GND
DD PACKAGE
12-LEAD (3mm
×
3mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 43°C/W
EXPOSED PAD (PIN 13)
MS PACKAGE
12-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 135°C/W
ORDER INFORMATION
LEAD FREE FINISH
LTC2461CDD#PBF
LTC2461IDD#PBF
LTC2461CMS#PBF
LTC2461IMS#PBF
LTC2463CDD#PBF
LTC2463IDD#PBF
LTC2463CMS#PBF
LTC2463IMS#PBF
TAPE AND REEL
LTC2461CDD#TRPBF
LTC2461IDD#TRPBF
LTC2461CMS#TRPBF
LTC2461IMS#TRPBF
LTC2463CDD#TRPBF
LTC2463IDD#TRPBF
LTC2463CMS#TRPBF
LTC2463IMS#TRPBF
PART MARKING*
LFGF
LFGF
2461
2461
LFGG
LFGG
2463
2463
PACKAGE DESCRIPTION
12-Lead Plastic (3mm × 3mm) DFN
12-Lead Plastic (3mm × 3mm) DFN
12-Lead Plastic MSOP
12-Lead Plastic MSOP
12-Lead Plastic (3mm × 3mm) DFN
12-Lead Plastic (3mm × 3mm) DFN
12-Lead Plastic MSOP
12-Lead Plastic MSOP
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
24613fa
2
LTC2461/LTC2463
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 2)
PARAMETER
Resolution (No Missing Codes)
Integral Nonlinearity
Offset Error
Offset Error Drift
Gain Error
Gain Error Drift
Includes Contributions of ADC and Internal Reference
Includes Contributions of ADC and Internal Reference
C-Grade
I-Grade
l
l
ELECTRICAL CHARACTERISTICS
CONDITIONS
(Note 3)
(Note 4)
MIN
l
l
l
TYP
1
2
5
0.02
±0.01
±2
±5
2.2
80
MAX
8
15
UNITS
Bits
LSB
LSB
LSB
LSB/°C
% of FS
ppm/°C
ppm/°C
µV
RMS
dB
16
LTC2461, 30Hz, LTC2463
LTC2461, 60Hz
±0.25
±10
Transition Noise
Power Supply Rejection DC
ANALOG INPUTS
specifications are at T
A
= 25°C.
PARAMETER
SYMBOL
V
IN+
V
IN–
V
IN
V
OR+
, V
UR+
V
OR–
, V
UR–
C
IN
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
CONDITIONS
LTC2463
LTC2463
LTC2461
V
IN–
= 0.625V (See Figure 3)
V
IN+
= 0.625V (See Figure 3)
V
IN
= GND or V
CC
(Note 8)
V
IN
= GND or V
CC
(Note 8)
l
l
l
l
l
MIN
0
0
0
TYP
MAX
V
REF
V
REF
V
REF
UNITS
V
V
V
LSB
LSB
pF
Positive Input Voltage Range
Negative Input Voltage Range
Input Voltage Range
Overrange/Underrange Voltage, IN
+
Overrange/Underrange Voltage, IN–
IN
+
, IN
–
, IN Sampling Capacitance
8
8
0.35
–10
–10
1.247
1
1
50
l
l
I
DC_LEAK(IN+, IN–, IN)
IN
+
, IN
–
DC Leakage Current (LTC2463)
IN DC Leakage Current (LTC2461)
I
CONV
V
REF
Input Sampling Current (Note 5)
REFOUT Output Voltage
10
10
1.253
±10
nA
nA
nA
V
ppm/°C
ppm/°C
dB
mA
µA
mV/mA
nV/√Hz
1.25
±2
±5
–90
REFOUT Voltage Temperature Coefficient (Note 9)
C-Grade
I-Grade
Reference Line Regulation
Reference Short Circuit Current
COMP Pin Short Circuit Current
Reference Load Regulation
Reference Output Noise Density
2.7V ≤ V
CC
≤ 5.5V
V
CC
= 5.5, Forcing REFOUT to GND
V
CC
= 5.5, Forcing REFOUT to GND
2.7V ≤ V
CC
≤ 5.5V, I
OUT
= 100μA Sourcing
,
,
C
COMP
= 0.1μF C
REFOUT
= 0.1μF At f = 1kHz
l
l
35
200
3.5
30
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C.
SYMBOL
V
CC
I
CC
PARAMETER
Supply Voltage
Supply Current
Conversion
Nap
Sleep
CONDITIONS
l
l
l
l
POWER REQUIREMENTS
MIN
2.7
TYP
MAX
5.5
UNITS
V
mA
µA
µA
1.5
800
0.2
2.5
1500
2
24613fa
3
LTC2461/LTC2463
I
2
C INPUTS AND OUTPUTS
SYMBOL
V
IH
V
IL
I
I
V
HYS
V
OL
I
IN
C
I
C
B
V
IH(A0)
V
IL(A0)
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Hysteresis of Schmidt Trigger Inputs
Low Level Output Voltage (SDA)
Input Leakage
Capacitance for Each I/O Pin
Capacitance Load for Each Bus Line
High Level Input Voltage for Address Pin
Low Level Input Voltage for Address Pin
(Note 3)
I = 3mA
0.1V
CC
≤ V
IN
≤ 0.9V
CC
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Notes 2, 7)
CONDITIONS
l
l
l
l
l
l
l
l
l
l
MIN
0.7V
CC
TYP
MAX
0.3V
CC
UNITS
V
V
µA
V
V
µA
pF
pF
V
V
–10
0.05V
CC
10
0.4
1
10
400
0.95V
CC
0.05V
CC
I
2
C TIMING CHARACTERISTICS
SYMBOL
t
CONV
f
SCL
t
HD(SDA,STA)
t
LOW
t
HIGH
t
SU(STA)
t
HD(DAT)
t
SU(DAT)
t
r
t
f
t
SU(STO)
t
BUF
t
OF
t
SP
PARAMETER
Conversion Time
SCL Clock Frequency
Hold Time (Repeated) START Condition
LOW Period of the SCL Pin
HIGH Period of the SCL Pin
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Notes 2, 7)
CONDITIONS
l
l
l
l
l
l
l
l
MIN
13
0
0.6
1.3
0.6
0.6
0
100
20 + 0.1C
B
20 + 0.1C
B
0.6
1.3
20 + 0.1C
B
TYP
16.6
MAX
23
400
UNITS
ms
kHz
ms
ms
ms
ms
Set-Up Time for a Repeated START Condition
Data Hold Time
Data Set-Up Time
Rise Time for SDA, SCL Signals
Fall Time for SDA, SCL Signals
Set-Up Time for STOP Condition
Bus Free Time Between a Stop and Start Condition
Output Fall Time V
IHMIN
to V
ILMAX
Input Spike Suppression
Bus Load C
B
= 10pF to
400pF (Note 6)
(Note 6)
(Note 6)
0.9
300
300
ms
ns
ns
ns
ms
ms
l
l
l
l
l
l
250
50
ns
ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to GND. V
CC
= 2.7V to 5.5V
unless otherwise specified.
Note 3:
Guaranteed by design, not subject to test.
Note 4:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
Guaranteed by design and test correlation.
Note 5:
Input sampling current is the average input current drawn from
the input sampling network while the LTC2461/LTC2463 are converting.
Note 6:
C
B
= capacitance of one bus line in pF
.
Note 7:
All values refer to V
IH(MIN
) and V
IL(MAX)
levels.
Note 8:
A positive current is flowing into the DUT pin.
Note 9:
Voltage temperature coefficient is calculated by dividing the
maximum change in output voltage by the specified temperature range.
FPGA/CPLD
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