CAT24C64
FEATURES
64-Kb I
2
C CMOS Serial EEPROM
DEVICE DESCRIPTION
The CAT24C64 is a 64-Kb CMOS Serial EEPROM
devices, internally organized as 128 pages of 64 bytes
each.
It features a 32-byte page write buffer and supports
both the Standard (100 kHz) as well as Fast (400 kHz)
I
2
C protocol.
External address pins make it possible to address up to
eight CAT24C64 devices on the same bus.
■
Supports Standard and Fast I
2
C Protocol
■
1.8 V to 5.5 V Supply Voltage Range
■
32-Byte Page Write Buffer
(1)
■
Hardware Write Protection for entire memory
■
Schmitt Triggers and Noise Suppression Filters
on I
2
C Bus Inputs (SCL and SDA).
■
Low power CMOS technology
■
1,000,000 program/erase cycles
■
100 year data retention
■
Industrial temperature range
■
RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
TDFN packages
Note:
(1) CAT24C64 Rev. D (Not Recommended for New Designs) has
64-Byte Page Write Buffer.
For Ordering Information details, see page 15.
PIN CONFIGURATION
PDIP (L)
SOIC (W)
TSSOP (Y)
TDFN (ZD2, VP2)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
FUNCTIONAL SYMBOL
VCC
SCL
A2, A1, A0
WP
CAT24C64
SDA
For the location of Pin 1, please consult the
corresponding package drawing.
PIN FUNCTIONS
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
Device Address
Serial Data
Serial Clock
Write Protect
Power Supply
Ground
VSS
* The Green & Gold seal identifies RoHS-compliant packaging, using NiPdAu
pre-plated lead frames.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1102, Rev. H
CAT24C64
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
-65°C to +150°C
-0.5 V to +6.5 V
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
< 2.5 V, I
OL
= 1.0 mA
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
Pin at GND or V
CC
-0.5
Min
Max
1
1
1
1
V
CC
x 0.3
Units
mA
mA
μA
μA
V
V
V
V
V
CC
x 0.7 V
CC
+ 0.5
0.4
0.2
PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
C
IN(3)
C
IN(3)
I
WP(5)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current
Conditions
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH
V
IN
> V
IH
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, V
CC
= 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power, as
the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull-down reverts to a weak current source.
Max
8
6
100
1
Units
pF
pF
μA
Doc. No. 1102, Rev. H
2
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C64
A.C. CHARACTERISTICS
(1)
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C.
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F(2)
t
SU:STO
t
BUF
t
AA
t
DH
T
i(2)
t
SU:WP
t
HD:WP
t
WR
t
PU(2, 3)
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Fast
Min
0.6
1.3
0.6
0.6
0
100
Max
400
Units
kHz
μs
μs
μs
μs
μs
ns
300
300
0.6
1.3
ns
ns
μs
μs
0.9
100
100
0
2.5
μs
ns
ns
μs
μs
5
1
ms
ms
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
Min
4
4.7
4
4.7
0
250
Max
100
1000
300
4
4.7
3.5
100
100
0
2.5
5
1
A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
≤
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3 mA (V
CC
≥
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1102, Rev. H
CAT24C64
POWER-ON RESET (POR)
Each CAT24C64 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into
Standby mode after V
CC
exceeds the POR trigger level
and will power down into Reset mode when V
CC
drops
below the POR trigger level. This bi-directional POR
behavior protects the device against ‘brown-out’ failure
following a temporary loss of power.
FUNCTIONAL DESCRIPTION
The CAT24C64 supports the Inter-Integrated Circuit
(I
2
C) Bus protocol. The protocol relies on the use of a
Master device, which provides the clock and directs bus
traffic, and Slave devices which execute requests. The
CAT24C64 operates as a Slave device. Both Master
and Slave can transmit or receive, but only the Master
can assign those roles.
I
2
C BUS PROTOCOL
The 2-wire I
2
C bus consists of two lines, SCL and SDA,
connected to the V
CC
supply via pull-up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics). During data transfer,
SDA must remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 1). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW
to HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8-bit Slave address.
For the CAT24C64, the first four bits of the Slave address
are set to 1010 (Ah); the next three bits, A
2
, A
1
and A
0
,
must match the logic state of the similarly named input
pins. The R/W bit tells the Slave whether the Master
R/
W
intends to read (1) or write (0) data (Figure 2).
Acknowledge
During the 9
th
clock cycle following every byte sent to
the bus, the transmitter releases the SDA line, allow-
ing the receiver to respond. The receiver then either
acknowledges (ACK) by pulling SDA LOW, or does not
acknowledge (NoACK) by letting SDA stay HIGH (Figure
3). Bus timing is illustrated in Figure 4.
PIN DESCRIPTION
SCL:
The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA:
The Serial Data I/O pin accepts input data and
delivers output data. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A
0
, A
1
and A
2
:
The Address inputs set the device ad-
dress that must be matched by the corresponding Slave
address bits. The Address inputs are hard-wired HIGH
or LOW allowing for up to eight devices to be used
(cascaded) on the same bus. When left floating, these
pins are pulled LOW internally.
WP:
When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin
is pulled LOW internally.
Doc. No. 1102, Rev. H
4
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C64
Figure 1. Start/Stop Timing
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ tAA)
ACK SETUP (≥ tSU:DAT)
Figure 4. Bus Timing
tF
tLOW
SCL
tSU:STA
SDA IN
tAA
SDA OUT
tDH
tBUF
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1102, Rev. H
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