CAT24WC66
64K-bit I
2
C Serial EEPROM with Partial Array Write Protection
FEATURES
400kHz I
2
C Bus
1.8V to 5.5V supply voltage range
Cascadable for up to eight devices
32-byte page write buffer
Self-timed write cycle with auto-clear
Schmitt trigger inputs for noise protection
Write protection
—
Top 1/4 array protected when WP at V
IH
1,000,000 program/erase cycles
100 year data retention
Industrial and automotive temperature ranges
RoHS-compliant packages
DESCRIPTION
The CAT24WC66 is a 64K-bit Serial CMOS EEPROM
internally organized as 8192 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24WC66
features a 32-byte page write buffer. The device
operates via the I
2
C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.
For Ordering Information details, see page 12.
PIN CONFIGURATION
DIP Package (L)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
SOIC Package (W, X)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
FUNCTIONAL SYMBOL
VCC
SCL
A2, A1, A0
WP
CAT24CW66
SDA
PIN FUNCTION
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
Power Supply
Ground
VSS
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I2C Bus Protocol.
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1037 Rev. J
CAT24WC66
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current
(3)
REABILITY CHARACTERISTICS
Symbol
NEND
(4)
TDR
ILTH
(4)
Ratings
–55 to +125
–65 to +150
–2.0 to V
CC
+ 2.0
–2.0 to 7.0
1.0
300
100
Units
ºC
ºC
V
V
W
ºC
mA
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
Volts
mA
VZAP
(4)
(4)(5)
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8V to 5.5V, unless otherwise specified.
Symbol
I
CC
I
SB(6)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= +3.0V)
Output Low Voltage(V
CC
= +1.8V)
I
OL
= 3.0 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 100kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Typ
Max
3
1
10
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
mA
µA
µA
µA
V
V
V
V
CAPACITANCE
T
A
= 25ºC, f = 1.0MHz, V
CC
= 5V
Symbol
C
I/O(4)
C
IN(4)
Parameter
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
Typ
Max
8
6
Units
pF
pF
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(6) Maximum standby current (ISB) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1037 Rev. J
2
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC66
AC CHARACTERISTICS
V
CC
= 1.8V to 5.5V, unless otherwise specified. Output Load is 1TTL Gate and 100pF.
Memory Read & Write Cycle Limits
Symbol
FSCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(1)
Parameter
Clock Frequency
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a
New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.8V - 2.5V
Min
Max
100
200
3.5
4.7
4
4.7
4
4.7
0
50
1
300
4
100
4.5V - 5.5V
Min
Max
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
t
F(1)
t
SU:STO
t
DH
Power-Up Timing
(1) (2)
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Notes:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
10
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to
remain high, and the device does not respond to its
slave address.
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1037 Rev. J
CAT24WC66
FUNCTIONAL DESCRIPTION
The CAT24WC66 supports the I
2
C Bus data transmission
protocol. This Inter-Integrated Circuit Bus protocol defines
any device that sends data to the bus to be a transmitter
and any device receiving data to be a receiver. The
transfer is controlled by the Master device which
generates the serial clock and all START and STOP
conditions for bus access. The CAT24WC66 operates as
a Slave device. Both the Master device and Slave device
can operate as either transmitter or receiver, but the
Master device controls which mode is activated.
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These pins are hardwired or left unconnected (for
hardware compatibility with CAT24WC16). When
hardwired, up to eight CAT24WC66 devices may be
addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the
default values are zeros.
WP:
Write Protect
This input, when tied to GND, allows write operations
to the entire memory. When this pin is tied to V
CC
, the
top 1/4 array of memory is write protected. When left
floating, memory is unprotected.
PIN DESCRIPTION
SCL:
Serial Clock
The serial clock input clocks all data transferred into
or out of the device.
SDA:
Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
Figure 1. Bus Timming
tF
tLOW
SCL
tSU:STA
SDA IN
tAA
SDA OUT
tHD:STA
tHD:DAT
tHIGH
tR
tLOW
tSU:DAT
tSU:STO
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1037 Rev. J
STOP BIT
4
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24WC66
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC66 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the
slave address byte, the CAT24WC66 monitors the
bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
address. The CAT24WC66 then performs a Read or
¯¯
Write operation depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
The CAT24WC66 responds with an acknowledge
after receiving a START condition and its slave
address. If the device has been selected along with a
write operation, it responds with an acknowledge after
receiving each 8-bit byte.
When the CAT24WC66 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC66 will continue to
transmit data. If no acknowledge is sent by the
Master, the device terminates data transmission and
waits for a STOP condition. The master must then
issue a stop condition to return the CAT24WC66 to
the standby power mode and place the device in a
known state.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 1010 (Fig. 5). The next three bits (A2, A1,
A0) are the device address bits; up to eight 64K
devices may to be connected to the same bus. These
bits must compare to the hardwired input pins, A2, A1
and A0. The last bit of the slave address specifies
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1037 Rev. J
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
