CAT25C01, CAT25C02, CAT25C04
1K/2K/4K SPI Serial CMOS EEPROM
FEATURES
I
10 MHz SPI compatible
I
1.8 to 5.5 volt operation
I
16-byte page write buffer
I
Hardware and software protection
I
Block write protection
DESCRIPTION
The CAT25C01/02/04 is a 1K/2K/4K Bit SPI Serial
CMOS EEPROM internally organized as 128x8/256x8/
512x8 bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25C01/02/04 features a 16-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The
HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C01/
02/04 is designed with software and hardware write
protection features including Block Write protection. The
device is available in 8-pin DIP, 8-pin SOIC and 8-pin
TSSOP packages.
– Protect 1/4, 1/2 or all of EEPROM array
I
Low power CMOS technology
I
SPI modes (0,0 & 1,1)
I
Industrial temperature range
I
1,000,000 program/erase cycles
I
100 year data retention
I
Self-timed write cycle
I
RoHS compliant
“
”
&
“
”
8-pin PDIP, SOIC and TSSOP packages
PIN CONFIGURATION
PDIP (L)
SOIC (V)
TSSOP (Y)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
D
s
i
Function
o
c
VCC
SCK
SI
HOLD
i
t
n
u
n
FUNCTIONAL SYMBOL
VCC
d
e
SI
CS
WP
a
P
s
t
r
CAT25C01
CAT25C02
CAT25C04
SO
HOLD
SCK
Serial Data Output
Serial Clock
VSS
Write Protect
+1.8V to +5.5V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
HOLD
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1105, Rev. B
CAT25C01, CAT25C02, CAT25C04
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature
Voltage on Any Pin with Respect to Ground
(1)
-65°C to +150°C
-0.5 V to +6.5 V
* Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
(2)
Symbol
N
END
(*)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
(*) Page Mode, V
CC
= 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40°C to 85°C, unless otherwise specified.
Symbol
I
CC
I
SB
I
L
V
IL
V
IH
V
OL1
V
OL2
Parameter
Supply Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Test Conditions
Read or Write at 5 MHz
All I/O Pins at GND or V
CC
,
CS
= V
CC
PIN IMPEDANCE CHARACTERISTICS
T
A
= 25°C, f = 1 MHz, V
CC
= 5 V
Symbol
C
IN(2)
C
IN(2)
Z
WPL
I
LWPH
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin
may undershoot to no less than -1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
D
s
i
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Low Impedance
WP Input High Leakage
o
c
i
t
n
Pin at GND or V
CC
V
CC
> 2.5 V, I
OL
= 3.0 mA
V
CC
> 1.8 V, I
OL
= 1.0 mA
u
n
d
e
Min
a
P
Years
Max
1
2
2
V
CC
x 0.3
0.4
0.2
s
t
r
Units
mA
µA
µA
V
V
V
V
-0.5
V
CC
x 0.7 V
CC
+ 0.5
Conditions
V
IN
= 0 V
V
IN
= 0 V
V
IN
< 0.5 V
V
IN
> V
CC
x 0.7
Min
Max
8
6
Units
pF
pF
kΩ
µA
5
70
2
Doc. No. 1105, Rev. B
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C01, CAT25C02, CAT25C04
A.C. CHARACTERISTICS
CAT25CXX-1.8
1.8V-5.5V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC(4)
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
WP
Setup Time
WP
Hold Time
0
100
100
5
Min.
50
50
250
250
DC
1
50
2
2
40
40
Max. Min.
20
20
75
75
DC
5
50
2
2
CAT25CXX
2.5V-5.5V
Max.
4.5V-5.5V
Min.
20
20
40
40
DC
10
Max.
ns
ns
ns
ns
Test
UNITS Conditions
50
2
Power-Up Timing
(1)(3)
Symbol
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source I
OL
max/I
OH
max; C
L
=50pF
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
(4) t
WC
is the time from the rising edge of
CS
after a valid write sequence to the end of the internal write cycle.
D
t
PUW
t
PUR
s
i
o
c
i
t
n
500
500
500
150
150
u
n
0
250
150
100
100
100
50
50
250
d
e
40
5
75
0
75
50
100
100
100
50
50
Max.
1
1
40
40
a
P
ns
µs
µs
ns
2
ns
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
s
t
r
C
L
= 50pF
(note 2)
75
50
Parameter
Units
ms
ms
Power-up to Read Operation
Power-up to Write Operation
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1105, Rev. B
CAT25C01, CAT25C02, CAT25C04
FUNCTIONAL DESCRIPTION
The CAT25C01/02/04 supports the SPI bus data
transmission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C01/02/04 to interface
directly with many of today’s popular microcontrollers.
The CAT25C01/02/04 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
CAT25010/20/40. Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the CAT25C01/02/04. During a read
cycle, data is shifted out on the falling edge of the serial
clock for SPI modes (0,0 & 1,1).
Figure 1. Sychronous Data Timing
V
IH
CS
V
IL
t
CSS
V
IH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
SI
VIL
VALID IN
V
OH
SO
V
OL
HI-Z
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Note:
(1) X=0 for CAT25C01, CAT25C02. X=A8 for CAT25C04.
D
s
i
o
c
Opcode
0000 0110
i
t
n
u
n
t
WL
t
RI
tFI
t
V
d
e
t
HO
t
CSH
a
P
t
DIS
HI-Z
s
t
r
t
CS
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
0000 0100
0000 0101
0000 0001
0000 X011
(1)
0000 X010
(1)
Doc. No. 1105, Rev. B
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C01, CAT25C02, CAT25C04
When
WP
is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP
going low while
CS
is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP
going low will
have no effect on any write operation to the status
register. The
WP
pin function is blocked when the WPEN
bit is set to 0. Figure 10 illustrates the
WP
timing
sequence during a write operation.
HOLD:
HOLD
Hold
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25C01/02/04. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C01/
02/04 and
CS
high disables the CAT25C01/02/04.
CS
high takes the SO output pin to high impedance and
forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25C01/
02/04 draws ZERO current in the Standby mode. A high
to low transition on
CS
is required prior to any sequence
being initiated. A low to high transition on
CS
after a valid
write sequence is what initiates an internal write cycle.
WP:
WP
Write Protect
WP
is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
STATUS REGISTER
7
WPEN
6
1
5
1
4
1
The
HOLD
pin is used to pause transmission to the
CAT25C01/20/40 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD
must be brought low while SCK
is low. The SO pin is in a high impedance state during
the time the part is paused, and transitions on the SI pins
will be ignored. To resume communication,
HOLD
is
brought high, while SCK is low. (HOLD should be held
high any time this function is not being used.)
HOLD
may
be tied high directly to V
CC
or tied to V
CC
through a
resistor. Figure 9 illustrates hold timing sequence.
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
0
0
1
1
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
D
s
i
o
c
0
1
0
1
i
t
n
Array Address
Protected
None
CAT25C01: 60-7F
CAT25C02: C0-FF
CAT25C04: 180-1FF
CAT25C01: 40-7F
CAT25C02: 80-FF
CAT25C04: 100-1FF
CAT25C01: 00-7F
CAT25C02: 00-FF
CAT25C04: 000-1FF
u
n
3
BP1
d
e
2
BP0
a
P
1
WEL
s
t
r
0
RDY
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1105, Rev. B
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