CAT25C08, CAT25C16
8K/16K SPI Serial CMOS EEPROM
FEATURES
I
10 MHz SPI compatible
I
1.8 to 5.5 volt operation
I
SPI modes (0,0 & 1,1)
I
32-byte page write buffer
I
Self-timed write cycle
I
Hardware and software protection
I
Block write protection
DESCRIPTION
The CAT25C08/16 is a 8K/16K Bit SPI Serial CMOS
EEPROM internally organized as 1024x8/2048x8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C08/
16 features a 32-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
required to access the device. The
HOLD
pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C08/16 is
designed with software and hardware write protection
features including Block Write protection. The device is
available in 8-pin DIP, 8-pin SOIC and 8-pin TSSOP
packages.
– Protect 1/4, 1/2 or all of EEPROM array
I
Low power CMOS technology
I
1,000,000 program/erase cycles
I
100 year data retention
I
Industrial temperature range
I
RoHS-compliant packages
For Ordering Information details, see page 15.
PIN CONFIGURATION
PDIP (L)
SOIC (V)
TSSOP (Y)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
FUNCTIONAL SYMBOL
VCC
SI
CS
WP
HOLD
CAT25C08
CAT25C16
SO
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
HOLD
SCK
Function
Serial Data Output
Serial Clock
Write Protect
Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
VSS
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1016, Rev. C
CAT25C08/16
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS(1)
.................. –1.5V to +V
CC
+1.5V
V
CC
with Respect to V
SS ................................
–0.5V to +6.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Typ.
Max.
Units
Cycles/Byte
Years
Volts
mA
1,000,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Limits
Symbol
I
CC1
I
CC2
I
SB(6)
I
LI
I
LO
V
IL(5)
V
IH(5)
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
V
CC
- 0.8
0.2
-1
V
CC
x 0.7
Min.
Typ.
Max.
5
3
1
2
3
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
V
V
2.5V≤V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V≤V
CC
<2.5V
I
OL
= 150µA
I
OH
= -100µA
V
OUT
= 0V to V
CC
,
CS = 0V
Test Conditions
V
CC
= 5V @ 5MHz
SO=open; CS=Vss
V
CC
= 5.5V
F
CLK
= 5MHz
CS
= V
CC
V
IN
= V
SS
or V
CC
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –1.5V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+1.5V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) V
ILMIN
and V
IHMAX
are reference values only and are not tested.
(6) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1016, Rev. C
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Max.
8
6
Units
pF
pF
Conditions
V
OUT
=0V
V
IN
=0V
A.C. CHARACTERISTICS
CAT25Cxx-1.8
1.8V-5.5V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC(3)
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
WPS
t
WPH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
CS
Setup Time
CS
Hold Time
WP
Setup Time
WP
Hold Time
500
500
500
150
150
0
250
150
100
100
100
50
50
100
100
10
250
0
75
50
100
100
100
50
50
Min.
50
50
250
250
DC
1
50
2
2
40
40
5
75
0
75
50
Max. Min.
20
20
75
75
DC
5
50
2
2
20
20
5
40
CAT25Cxx
2.5V-5.5V
Max.
4.5V-5.5V
Min.
20
20
40
40
DC
10
20
2
2
Max.
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 50pF
(2)
Test
UNITS Conditions
Power-Up Timing
(4)(5)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) AC Test Conditions:
Input Pulse Voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C
L
= 50pF
(3) t
WC
is the time from the rising edge of
CS
after a valid write sequence to the end of the internal write cycle.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1016, Rev. C
3
CAT25C08/16
FUNCTIONAL DESCRIPTION
The CAT25C08/16 supports the SPI bus data transmis-
sion protocol. The synchronous Serial Peripheral Inter-
face (SPI) helps the CAT25C08/16 to interface directly
with many of today’s popular microcontrollers. The
CAT25C08/16 contains an 8-bit instruction register.
(The instruction set and the operation codes are de-
tailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C08/16. Input data is latched on the rising edge of the
serial clock for SPI modes (0, 0 & 1, 1).
SO:
Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C08/16. During a read cycle,
data is shifted out on the falling edge of the serial clock
for SPI modes (0,0 & 1,1).
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
Figure 1. Sychronous Data Timing
V
IH
t
CS
CS
V
IL
V
IH
t
CSS
t
CSH
SCK
V
IL
t
SU
V
IH
t
WH
t
H
t
WL
SI
VIL
VALID IN
t
RI
tFI
t
V
V
OH
t
HO
t
DIS
HI-Z
SO
V
OL
HI-Z
Note: Dashed Line= mode (1, 1) – – – – –
INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Doc. No. 1016, Rev. C
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C08/16
and the 25C08/16. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK for SPI modes (0,0 & 1,1) .
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C08/
16 and
CS
high disables the CAT25C08/16.
CS
high
BYTE ADDRESS
Device
CAT25C08
CAT25C16
STATUS REGISTER
7
WPEN
6
0
5
1
4
0
Address Significant Bits
A9 - A0
A10 - A0
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway) The CAT25C08/16 draws
ZERO current in the Standby mode. A high to low
transition on
CS
is required prior to any sequence being
initiated. A low to high transition on
CS
after a valid write
sequence is what initiates an internal write cycle.
Address Don't Care Bits
A15 - A10
A15 - A11
# Address Clock Pulse
16
16
3
BP1
2
BP0
1
WEL
0
RDY
BLOCK PROTECTION BITS
Status Register Bits
BP1
BP0
0
0
1
1
0
1
0
1
Array Address
Protected
None
25C08: 0300-03FF
25C16: 0600-07FF
25C08: 0200-03FF
25C16: 0400-07FF
25C08: 0000-03FF
25C16: 0000-07FF
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 1016, Rev. C
FPGA/CPLD
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