CAT28C17A
16K-Bit CMOS PARALLEL EEPROM
FEATURES
■
Fast Read Access Times: 200 ns
■
Low Power CMOS Dissipation:
■
End of Write Detection:
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
–Active: 25 mA Max.
–Standby: 100
µ
A Max.
■
Simple Write Operation:
–DATA Polling
DATA
–RDY/BSY Pin
BSY
■
Hardware Write Protection
■
CMOS and TTL Compatible I/O
■
10,000 Program/Erase Cycles
■
10 Year Data Retention
■
Commercial,Industrial and Automotive
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
■
Fast Write Cycle Time: 10ms Max
Temperature Ranges
DESCRIPTION
The CAT28C17A is a fast, low power, 5V-only CMOS
parallel EEPROM organized as 2K x 8-bits. It requires
a simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware.
DATA
Polling and a RDY/BSY pin signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C17A features hardware write protection.
The CAT28C17A is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 28-pin DIP and SOIC or 32-pin PLCC pack-
ages.
BLOCK DIAGRAM
A4–A10
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
2,048 x 8
EEPROM
ARRAY
VCC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
TIMER
DATA POLLING
& RDY/BUSY
I/O0–I/O7
A0–A3
ADDR. BUFFER
& LATCHES
COLUMN
DECODER
RDY/BUSY
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1075, Rev. B
CAT28C17A
PIN CONFIGURATION
DIP Package (P, L)
RDY/BUSY
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
NC
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
SOIC Package (J,W) (K, X)
RDY/BUSY
NC
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
NC
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
PLCC Package (N, G)
A7
NC
RDY/BUSY
4 3 2 1 32 31 30
29
28
27
26
TOP VIEW
25
24
23
A8
A9
NC
NC
OE
A10
CE
I/O7
I/O6
12
22
13
21
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
PIN FUNCTIONS
Pin Name
A
0
–A
10
I/O
0
–I/O
7
RDY/BUSY
CE
OE
WE
V
CC
V
SS
NC
Function
Address Inputs
Data Inputs/Outputs
Ready/BUSY Status
Chip Enable
Output Enable
Write Enable
5V Supply
Ground
No Connect
MODE SELECTION
Mode
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
H
X
CE
L
L
L
X
H
WE
H
OE
L
H
H
X
H
I/O
D
OUT
D
IN
D
IN
High-Z
High-Z
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(1)
C
IN(1)
Test
Input/Output Capacitance
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1075, Rev. B
2
NC
VCC
WE
NC
CAT28C17A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(2)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(3)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
T
DR(1)
V
ZAP(1)
I
LTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
10,000
10
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= 5V
±10%,
unless otherwise specified.
Limits
Symbol
I
CC
I
CCC(5)
I
SB
I
SBC(6)
I
LI
I
LO
V
IH(6)
V
IL(5)
V
OH
V
OL
V
WI
Parameter
V
CC
Current (Operating, TTL)
V
CC
Current (Operating, CMOS)
V
CC
Current (Standby, TTL)
V
CC
Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
3.0
–10
–10
2
–0.3
2.4
0.4
Min.
Typ.
Max.
35
25
1
100
10
10
V
CC
+0.3
0.8
Units
mA
mA
mA
µA
µA
µA
V
V
V
V
V
I
OH
= –400µA
I
OL
= 2.1mA
Test Conditions
CE = OE = V
IL
,
f = 1/t
RC
min, All I/O’s Open
CE = OE = V
ILC
,
f = 1/t
RC
min, All I/O’s Open
CE = V
IH
, All I/O’s Open
CE = V
IHC
,
All I/O’s Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CE = V
IH
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+1V.
(5) V
ILC
= –0.3V to +0.3V.
(6) V
IHC
= V
CC
–0.3V to V
CC
+0.3V.
3
Doc. No. 1075, Rev. B
CAT28C17A
A.C. CHARACTERISTICS, Read Cycle
V
CC
= 5V
±10%,
unless otherwise specified.
28C17A-20
Symbol
t
RC
t
CE
t
AA
t
OE
t
LZ(1)
t
OLZ(1)
t
HZ(1)(2)
t
OHZ(1)(2)
t
OH(1)
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
Output Hold from Address Change
0
0
0
55
55
Parameter
Min.
200
200
200
80
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1. A.C. Testing Input/Output Waveform(3)
2.4 V
INPUT PULSE LEVELS
0.45 V
0.8 V
2.0 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
(3) Input rise and fall times (10% and 90%) < 10 ns.
Doc. No. 1075, Rev. B
4
CAT28C17A
A.C. CHARACTERISTICS, Write Cycle
V
CC
= 5V
±10%,
unless otherwise specified.
28C17A-20
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW(2)
t
OES
t
OEH
t
WP(2)
t
DS
t
DH
t
DL
t
INIT(1)
t
DB
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Data Latch Time
Write Inhibit Period After Power-up
Time to Device Busy
10
100
0
0
150
15
15
150
50
10
50
5
20
80
Parameter
Min.
Max.
10
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
5
Doc. No. 1075, Rev. B
FPGA/CPLD
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