电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

CAT5114LI-50TE13

产品描述10K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 32 POSITIONS, PDSO8
产品类别半导体    逻辑   
文件大小50KB,共7页
制造商Catalyst
官网地址http://www.catalyst-semiconductor.com/
下载文档 详细参数 全文预览

CAT5114LI-50TE13概述

10K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 32 POSITIONS, PDSO8

10K 数字电位器, 递增/递减控制接口, 32 位置, PDSO8

CAT5114LI-50TE13规格参数

参数名称属性值
功能数量1
端子数量8
最大工作温度85 Cel
最小工作温度-40 Cel
额定供电电压3 V
额定总电阻10000 ohm
加工封装描述铅 AND HALOGEN FREE, SOIC-8
无铅Yes
欧盟RoHS规范Yes
中国RoHS规范Yes
状态ACTIVE
工艺CMOS
包装形状矩形的
包装尺寸SMALL OUTLINE
表面贴装Yes
端子形式GULL WING
端子间距1.27 mm
端子涂层MATTE 锡
端子位置
包装材料塑料/环氧树脂
温度等级INDUSTRIAL
转换器的类型数字电位器
电阻率线性
控制接口INCREMENT/DECREMENT
方位数32
最大电阻容差20 %
额定温度系数300 ppm/Cel
最大终端电阻电压3 V
最小终端电阻电压0.0 V

文档预览

下载PDF文档
CAT5112
32-Tap Digitally Programmable Potentiometer (DPP™)
with Buffered Wiper
FEATURES
s
32-position linear taper potentiometer
s
Non-volatile NVRAM wiper storage;
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
APPLICATIONS
s
Automated product calibration
s
Remote control adjustments
s
Offset, gain and zero control
s
Tamper-proof calibrations
s
Contrast, brightness and volume controls
s
Motor controls and feedback systems
s
Programmable analog functions
buffered wiper
s
Low power CMOS technology
s
Single supply operation: 2.5V-6.0V
s
Increment up/down serial interface
s
Resistance values: 10kΩ, 50kΩ and 100kΩ
Ω,
s
Available in PDIP, SOIC, TSSOP and MSOP packages
DESCRIPTION
The CAT5112 is a single digitally programmable
potentiometer (DPP™) designed as a electronic
replacement for mechanical potentiometers and trim
pots. Ideal for automated adjustments on high volume
production lines, they are also well suited for
applications where equipment requiring periodic
adjustment is either difficult to access or located in a
hazardous or remote environment.
The CAT5112 contains a 32-tap series resistor array
connected between two terminals R
H
and R
L
. An up/
down counter and decoder that are controlled by three
input pins, determines which tap is connected to the
wiper, R
WB
. The CAT5112 wiper is buffered by an op
amp that operates rail to rail. The wiper setting, stored in
non-volatile NVRAM memory, is not lost when the de-
vice is powered down and is automatically recalled when
power is returned. The wiper can be adjusted to test new
FUNCTIONAL DIAGRAM
V
CC
RH
system values without effecting the stored
setting. Wiper-control of the CAT5112 is
accomplished with three input control pins,
CS,
U/D,
and
INC.
The
INC
input increments the wiper in the
direction which is determined by the logic state of
the U/D input. The
CS
input is used to select the
device and also store the wiper position prior to
power down.
The digitally programmable potentiometer can be
used as a buffered voltage divider. For applications
where the potentiometer is used as a 2-terminal variable
resistor, please refer to the CAT5114. The buffered
wiper of the CAT5112 is not compatible with that appli-
cation. DPPs bring variability and programmability to a
broad range of applications and are used primarily to
control, regulate or adjust a characteristic or parameter
of an analog circuit.
R
H
U/D
INC
CS
Power On Recall
+
>
Control
and
Memory
+
RWB
R
WB
R
L
RL
V
SS
Electronic Potentiometer
Implementation
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 2002, Rev. L
1
SOSO不在的日子里
今天是EEWORLD大拿soso休年假第三天,大家都好想念她啊! 论坛里网友呼声不断: 在每日签到帖子里:aiwenzx连续两天都问到“soso 还在休假吗?”、 “soso还没回来吗?” Melinda123 ......
EEW 聊聊、笑笑、闹闹
内核开发人员Jens Axboe专访
原文地址 jens Axboe has been involved with Linux since 1993. 30 years old, he lives in Copenhagen, Denmark, and works as a Linux Kernel developer for Oracle. His block layer rew ......
白丁 聊聊、笑笑、闹闹
第一次的抉择......
小弟接到两份Offer: 1.做手机驱动(中低端MTK),这个偏硬的,手机设计行业的发展前景如何 2.做网络存储的,用Linux,这个好像偏软点,网络存储的这个行业发展前景是不是要好一些呀? 待遇 ......
ROLY1024 嵌入式系统
【Silicon Labs 开发套件评测】基于深度学习的tensorflow应用代码分析
基于深度学习的tensorflow应用代码分析 1. Silab这个版本的SDK最有趣的更新就是把深度学习框架tensorflow引入嵌入式开发中。本次还提供了一个范例程序,tensorflow_lite_micro_helloworld, ......
北方 Silicon Labs测评专区
高速信号信号完整性问题
图中右侧是光电转换模块,左侧是处理器差分信号输入输出端。信号速率为10G/s。有如下问题: 1.RD,TD线在serdes端都做了阻抗匹配处理,为何采用两种不同的匹配方式?单向信号是否只在单端做匹 ......
dlcnight PCB设计

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 869  260  2841  305  1162  18  6  58  7  24 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved