CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
FEATURES
s
SPI bus compatible
s
Low power CMOS technology
s
2.5V to 6.0V operation
s
Self-timed write cycle with auto-clear
s
Hardware reset pin
s
Hardware and software write protection
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
s
Commercial, industrial and automotive
temperature ranges
s
Power-up inadvertant write protection
s
RDY/BSY pin for end-of-write indication
BSY
s
1,000,000 program/erase cycles
s
100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst’s advanced CMOS
PIN CONFIGURATION
DIP Package (P, L)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
RDY/BUSY
RESET
GND
RDY/BUSY
VCC
CS
SK
PIN FUNCTIONS
Pin Name
CS
SK
DI
D
DO
V
CC
GND
RESET
s
i
o
c
Chip Select
Clock Input
Ground
Reset
i
t
n
1
2
3
4
8
7
6
5
CS
SK
1
2
3
4
8
7
6
5
DI
DO
SOIC Package (J, W)
u
n
RESET
GND
DO
DI
VCC
RDY/BUSY
RESET
GND
EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
d
e
CS
SK
DI
DO
1
2
3
4
RDY/BUSY
VCC
CS
SK
1
2
3
4
VCC
a
P
8
7
6
5
8
7
6
5
RESET
GND
DO
DI
s
t
r
TSSOP Package (U, Y)
VCC
RDY/BUSY
RESET
GND
SOIC Package (S, V)
TSSOP Package (UR, YR)
BLOCK DIAGRAM
GND
Function
MEMORY ARRAY
64/128/256 x 16
ADDRESS
DECODER
Serial Data Input
Serial Data Output
+2.5V to +6.0V Power Supply
DI
RESET
CS
MODE DECODE
LOGIC
DATA
REGISTER
OUTPUT
BUFFER
SK
CLOCK
GENERATOR
DO
RDY/BUSY
RDY/BUSY
Ready/BUSY Status
64LC10/20/40 F02
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1021, Rev. C
CAT64LC10/20/40
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
............ –2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
CAPACITANCE
(T
A
= 25°C, f= 1.0 MHz, V
CC
=6.0V)
Symbol
C
I/O(3)
C
IN(3)
Test
Input/Output Capacitance (DO, RDY/BSY)
Input Capacitance (CS, SK, DI, RESET)
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
D
Doc. No. 1021, Rev. C
s
i
o
c
i
t
n
u
n
d
e
Max.
8
6
MIL-STD-883, Test Method 3015
JEDEC Standard 17
a
P
Units
pF
pF
s
t
r
Conditions
V
I/O
= 0V
V
IN
= 0V
2
CAT64LC10/20/40
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Limits
Sym.
I
CC
Parameter
Operating Current
2.5V
Min.
Typ.
Max.
0.4
1
2
3
3
2
10
–0.1
V
CC
x 0.7
–0.1
V
CC
x 0.8
Units
mA
mA
mA
mA
µA
µA
µA
V
V
V
V
V
V
V
0.4
0.4
V
V
I
OH
= –10µA
I
OH
= –10µA
I
OH
= –400µA
I
OL
= 10µA
I
OL
= 2.1mA
Test Conditions
f
SK
= 250 kHz
f
SK
= 1 MHz
EWEN, EWDS, READ 6.0V
I
CCP
Program Current
2.5V
6.0V
I
SB(1)
I
LI
I
LO
V
IL
V
IH
V
IL
V
IH
Standby Current
Input Leakage Current
Output Leakage Current
Low Level Input Voltage, DI
High Level Input Voltage, DI
Low Level Input Voltage,
CS,
SK, RESET
High Level Input Voltage,
CS,
SK, RESET
2.5V
6.0V
V
OH(1)
High Level Output Voltage
V
OL(1)
Low Level Output Voltage
Note:
(1) V
OH
and V
OL
spec applies to READY/BUSY pin also
D
s
i
o
c
i
t
n
2.5V
6.0V
V
CC
– 0.3
V
CC
– 0.3
2.4
u
n
d
e
V
CC
+ 0.5
V
CC
x 0.2
V
CC
+ 0.5
V
CC
x 0.3
a
P
V
IN
= GND or V
CC
CS = V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
s
t
r
3
Doc. No. 1021, Rev. C
CAT64LC10/20/40
A.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(2)
t
CSMIN
t
SKHI
Parameter
CS
Setup Time
CS
Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High Impendance
Minimum
CS
High Time
Minimum SK High Time
2.5V
4.5V–6.0V
t
SKLOW
Minimum SK Low Time
2.5V
250
Min.
100
100
200
200
Typ.
Max.
Units
ns
t
SV
f
SK
Output Delay to Status Valid
Maximum Clock Frequency
t
RESS
t
RESMIN
t
RESH
t
RC
Reset to
CS
Setup Time
Minimum RESET High Time
RESET to READY Hold Time
Write Recovery
POWER-UP TIMING
(1)(3)
Symbol
t
PUR
t
PUW
WRITE CYCLE LIMIITS
Symbol
t
WR
Parameter
Program Cycle Time
2.5V
4.5V–6.0V
Min.
Max.
10
5
Units
ms
D
s
i
o
c
i
t
n
u
n
2.5V
4.5V–6.0V
4.5V–6.0V
d
e
400
1000
400
250
1000
0
250
0
100
Min.
1000
a
P
300
500
500
300
s
t
r
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
ns
ns
ns
ns
Parameter
Max.
10
1
Units
µs
ms
Power-Up to Read Operation
Power-Up to Program Operation
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) This parameter is sampled but not 100% tested.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 1021, Rev. C
4
CAT64LC10/20/40
INSTRUCTION SET
Instruction
Read
64LC10
64LC20
64LC40
Write
64LC10
64LC20
64LC40
Write Enable
Write Disable
[Write All Locations]
(1)
Opcode
10101000
10101000
10101000
10100100
10100100
10100100
10100011
10100000
10100001
Address
A5 A4 A3 A2 A1 A0 0
A6 A5 A4 A3 A2 A1 A0
0
0
Data
D15 - D0
D15 - D0
D15 - D0
D15 - D0
A7 A6 A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0 0
A6 A5 A4 A3 A2 A1 A0
0
0
D15 - D0
D15 - D0
A7 A6 A5 A4 A3 A2 A1 A0
XXXXXXXX
XXXXXXXX
XXXXXXXX
Figure 1. A.C. Testing Input/Output Waveform
(2)(3(4)
(C
L
= 100 pF)
VCC x 0.8
INPUT PULSE LEVELS
VCC x 0.2
VCC x 0.7
Note:
(1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
(2) Input Rise and Fall Times (10% to 90%) < 10 ns.
(3) Input Pulse Levels = V
CC
x 0.2 and V
CC
x 0.8.
(4) Input and Output Timing Reference = V
CC
x 0.3 and V
CC
x 0.7.
D
s
i
o
c
i
t
n
u
n
VCC x 0.3
d
e
REFERENCE POINTS
a
P
D15–D0
s
t
r
5
Doc. No. 1021, Rev. C
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
