CAT93C46
1-Kb Microwire Serial EEPROM
FEATURES
s
High speed operation: 2MHz
s
1.8V to 5.5V supply voltage range
s
Selectable x8 or x16 memory organization
s
Self-timed write cycle with auto-clear
s
Software write protection
s
Power-up inadvertant write protection
s
Low power CMOS technology
s
1,000,000 Program/erase cycles
s
100 year data retention
s
Industrial temperature ranges
s
RoHS-compliant 8-pin PDIP, SOIC, TSSOP and
DESCRIPTION
The CAT93C46 is a 1K-bit Serial EEPROM memory
device which is configured as either 64 registers of 16
bits (ORG pin at V
CC
) or 128 registers of 8 bits (ORG pin
at GND). Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT93C46 features a
self-timed internal write with auto-clear. On-chip Power-
On Reset circuit protects the internal logic against
powering up in the wrong state.
For Ordering Information details, see page 13.
8-pad TDFN packages
PIN CONFIGURATION
PDIP (L)
SOIC (V, X)
TSSOP (Y)
TDFN (VP2)
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
NC
VCC
CS
SK
FUNCTIONAL SYMBOL
V
CC
SOIC (W)
ORG
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
CS
SK
DI
CAT93C46
DO
GND
PIN FUNCTIONS
Pin Name
CS
SK
DI
DO
V
CC
GND
ORG
NC
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
Note: When the ORG pin is connected to VCC, the x16 organization
is selected. When it is connected to ground, the x8 organization is
selected. If the ORG pin is left unconnected, then an internal pullup
device will select the x16 organization.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1106, Rev. F
1
CAT93C46
ABSOLUTE MAXIMUM RATINGS
(1)
Storage Temperature
Voltage on Any Pin with Respect to Ground
(2)
-65°C to +150°C
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR
Parameter
Endurance
Data Retention
Min
1,000,000
100
Units
Program/ Erase Cycles
Years
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, T
A
=-40°C to +85°C, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current
(Write)
Power Supply Current
(Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz
V
CC
= 5.0V
f
SK
= 1MHz
V
CC
= 5.0V
V
IN
=GND or V
CC,
CS =GND
ORG=GND
V
IN
=GND or V
CC,
CS =GND
ORG=Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CS = GND
4.5V
≤
V
CC
< 5.5V
4.5V
≤
V
CC
< 5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
< 5.5V
I
OL
= 2.1mA
4.5V
≤
V
CC
< 5.5V
I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V
I
OL
= 1mA
1.8V
≤
V
CC
< 4.5V
I
OH
= -100µA
V
CC
- 0.2
2.4
0.2
-0.1
2
0
V
CC
x 0.7
Min
Max
1
500
2
1
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+1
0.4
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than V
CC
+0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than V
CC
+1.5V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Block Mode, V
CC
= 5V, 25°C
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
2
Doc No. 1106, Rev. F
CAT93C46
PIN CAPACITANCE
T
A
=25°C, f=1MHz, V
CC
=5V
Symbol
C
OUT(1)
C
IN(1)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
=0V
V
IN
=0V
Min
Typ
Max
5
5
Units
pF
pF
A.C. CHARACTERISTICS
(2)
V
CC
= +1.8V to +5.5V, T
A
=-40°C to +85°C, unless otherwise specified.
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2000
Min
50
0
100
100
0.25
0.25
100
5
Max
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
POWER-UP TIMING
(1)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
NOTES:
(1) These parameters are tested initially and after a design or process change that affects the parameter according to
appropriate AEC-Q100 and JEDEC test methods.
(2) Test conditions according to “AC Test Conditions” table.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1106, Rev. F
CAT93C46
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
Current Source I
OLmax
/I
OHmax
; C
L
=100pF
DEVICE OPERATION
The CAT93C46 is a 1024-bit nonvolatile memory in-
tended for use with industry standard microprocessors.
The CAT93C46 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase opera-
tions of the device. When organized as X8, seven 10-bit
instructions control the reading, writing and erase
operations of the device. The CAT93C46 operates on
a single power supply and will generate on chip the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status during a write operation. The serial
communication protocol follows the timing shown in
Figure 1.
The ready/busy status can be determined after the start
of internal write cycle by selecting the device (CS high)
and polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the rising edge of the clock (SK). Placing the DO pin
into the high impedance state is recommended in appli-
cations where the DI pin and the DO pin are to be tied
together to form a common DI/O pin. The Ready/Busy
INSTRUCTION SET
Address
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
x8
A6-A0
A6-A0
A6-A0
11XXXXX
00XXXXX
10XXXXX
01XXXXX
flag can be disabled only in Ready state; no change is
allowed in Busy state.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit address
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organization).
Read
Upon receiving a READ command (Figure 2) and an
address (clocked into the DI pin), the DO pin of the
CAT93C46 will come out of the high impedance state
and, after sending an initial dummy zero bit, will begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t
PD0
or t
PD1
).
Erase/Write Enable and Disable
The CAT93C46 powers up in the write disable state. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled,
it will remain enabled until power to the device is removed,
or the EWDS instruction is sent. The EWDS instruction
can be used to disable all CAT93C46 write and erase
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
The EWEN and EWDS instructions timing is shown in
Figure 3.
Data
x8
x16
Comments
Read Address AN– A0
Clear Address AN– A0
D7-D0
D15-D0
Write Address AN– A0
Write Enable
Write Disable
Clear All Addresses
D7-D0
D15-D0
Write All Addresses
Doc No. 1106, Rev. F
x16
A5-A0
A5-A0
A5-A0
11XXXX
00XXXX
10XXXX
01XXXX
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
CAT93C46
Figure 1. Sychronous Data Timing
tSKHI
SK
tDIS
DI
tCSS
CS
tDIS
DO
tPD0,tPD1
DATA VALID
tCSMIN
VALID
VALID
tDIH
tSKLOW
tCSH
Figure 2. Read Instruction Timing
SK
tCSMIN
CS
STANDBY
AN
DI
1
1
0
tHZ
0
DN
DN—
1
D1
D0
HIGH-Z
AN—1
A0
DO
HIGH-Z
tPD0
Figure 3. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE=11
DISABLE=00
© 2007 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1106, Rev. F
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