CAT93C76 (Rev. A)
8K-Bit Microwire Serial EEPROM
FEATURES
High speed operation: 3MHz @ V
CC
≥
2.5V
Low power CMOS technology
1.8 to 5.5 volt operation
Selectable x8 or x16 memory organization
Self-timed write cycle with auto-clear
Software write protection
Power-up inadvertant write protection
1,000,000 Program/erase cycles
100 year data retention
Industrial and extended temperature ranges
Sequential read
“Green” package option available
DESCRIPTION
The CAT93C76 is an 8K-bit Serial EEPROM memory
device which is configured as either registers of 16
bits (ORG pin at V
CC
or Not Connected) or 8 bits
(ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The
CAT93C76 is manufactured using Catalyst’s
advanced CMOS EEPROM floating gate technology.
The device is designed to endure 1,000,000
program/erase cycles and has a data retention of 100
years. The device is available in 8-pin PDIP, SOIC,
TSSOP and 8-pad TDFN packages.
PIN CONFIGURATION
PDIP (L), SOIC (V)
TSSOP (Y), TDFN (ZD4)
CS
SK
DI
DO
1
2
3
4
8 V
CC
7 NC
6 ORG
5 GND
FUNCTIONAL SYMBOL
V
CC
ORG
CS
SK
DI
DO
GND
PIN FUNCTION
Pin Name
CS
SK
DI
DO
V
CC
GND
ORG
NC
Function
Chip Select
Serial Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
For Ordering Information details, see page 12.
Note:
When the ORG pin is connected to V
CC
, x16 organization is
selected. When it is connected to ground, x8 organization
is selected. If the ORG pin is left unconnected, then an
internal pull-up device will select x16 organization.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1090 Rev. B
CAT93C76 (Rev. A)
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground
(2)
V
CC
with Respect to Ground
Lead Soldering Temperature (10 seconds)
Output Short Circuit Current
(3)
Ratings
–55 to +125
–65 to 150
-2.0 to +V
CC
+2.0
-2.0 to +7.0
300
100
Units
ºC
ºC
V
V
ºC
mA
RELIABILITY CHARACTERISTICS
(3)
Symbol
N
END(4)
T
DR(4)
V
ZAP(4)
I
LTH(4)(5)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Units
Cycles/Byte
Years
V
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
I
LORG
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current (Write)
Power Supply Current (Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
ORG Pin Leakage Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1MHz; V
CC
= 5.0V
f
SK
= 1MHz; V
CC
= 5.0V
CS = 0V ORG = GND
CS = 0V ORG = Float or V
CC
V
IN
= 0V to V
CC
V
OUT
= 0V to V
CC
, CS = 0V
ORG = GND or ORG = V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
< 4.5V
1.8V
≤
V
CC
< 4.5V
4.5V
≤
V
CC
≤
5.5V; I
OL
= 2.1mA
4.5V
≤
V
CC
≤
5.5V; I
OH
= -400µA
1.8V
≤
V
CC
< 4.5V; I
OL
= 100µA
1.8V
≤
V
CC
< 4.5V; I
OH
= -100µA
Min
Typ
1
300
2
0
(6)
0
(6)
0
(6)
1
Max
3
500
10
10
10
10
10
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
Units
mA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
-0.1
2
0
V
CC
x 0.7
2.4
0.1
V
CC
- 0.2
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20ns.
(3) Output shorted for no more than one second.
(4) These parameters are tested initially and after a design or process change that affects the parameter.
(5) Latch-up protection is provided for stresses up to 100 mA on I/O pins from –1V to V
CC
+1V.
(6) 0µA is defined as less than 900nA.
Doc. No. MD-1090 Rev. B
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C76 (Rev. A)
PIN CAPACITANCE
(1)
Symbol
C
OUT
C
IN
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0V
V
IN
= 0V
Min
Typ
Max
5
5
Units
pF
pF
INSTRUCTION SET
(2)
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit
1
1
1
1
1
1
1
Address
Opcode
10
11
01
00
00
00
00
x8
A10-A0
A10-A0
A10-A0
11XXXXXXXXX
00XXXXXXXXX
10XXXXXXXXX
01XXXXXXXXX
x16
A9-A0
A9-A0
A9-A0
11XXXXXXXX
00XXXXXXXX
10XXXXXXXX
01XXXXXXXX
D7-D0
D15-D0
D7-D0
D15-D0
x8
Data
x16
Comments
Read Address AN– A0
Clear Address AN– A0
Write Address AN– A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
A.C. CHARACTERISTICS
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
(1)(4)
Test
Conditions
V
CC
= 1.8V - 2.5V
Min
100
0
100
100
250
Max
V
CC
= 2.5V - 5.5V
Min
50
0
50
50
150
150
100
5
150
150
150
Max
Units
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
100
DC
3000
ns
kHz
C
L
= 100pF
(3)
250
150
5
200
250
250
250
DC
1000
POWER-UP TIMING
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
Notes:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or “0” for READ,
WRITE and ERASE commands.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
(4) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-1090 Rev. B
CAT93C76 (Rev. A)
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
≤
50ns
0.4V to 2.4V
0.8V, 2.0V
0.2V
CC
to 0.7V
CC
0.5V
CC
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
1.8V
≤
V
CC
≤
4.5V
1.8V
≤
V
CC
≤
4.5V
DEVICE OPERATION
The CAT93C76 is a 8192-bit nonvolatile memory
intended for use with industry standard micropro-
cessors. The CAT93C76 can be organized as either
registers of 16 bits or 8 bits. When organized as X16,
seven 13-bit instructions control the read, write and
erase operations of the device. When organized as
X8, seven 14-bit instructions control the read, write
and erase operations of the device. The CAT93C76
operates on a single power supply and will generate
on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked
into the DI pin on the rising edge of the clock (SK).
The DO pin is normally in a high impedance state
except when reading data from the device, or when
checking the ready/busy status after a write operation.
The ready/busy status can be determined after the
start of a write operation by selecting the device (CS
high) and polling the DO pin; DO low indicates that the
write operation is not completed, while DO high
indicates that the device is ready for the next
instruction. If necessary, the DO pin may be placed
back into a high impedance state during chip select by
shifting a dummy “1” into the DI pin. The DO pin will
enter the high impedance state on the falling edge of
the clock (SK). Placing the DO pin into the high
impedance state is recommended in applications
where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The most significant bit of the address
is “don’t care” but it must be present.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C76
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting
out the data addressed (MSB first). The output data
bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t
PD0
or t
PD1
).
For the CAT93C76, after the initial data word has
been shifted out and CS remains asserted with the SK
clock continuing to toggle, the device will
automatically increment to the next address and shift
out the next data word in a sequential READ mode.
As long as CS is continuously asserted and SK
continues to toggle, the device will keep incrementing
to the next address automatically until it reaches the
end of the address space, then loops back to address
0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All
subsequent data words will follow without a dummy
zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for
a minimum of t
CSMIN
. The falling edge of CS will start
the self clocking clear and data store cycle of the
memory location specified in the instruction. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C76 can be
determined by selecting the device and polling the DO
pin. Since this device features Auto-Clear before
write, it is NOT necessary to erase a memory location
before it is written into.
Doc. No. MD-1090 Rev. B
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT93C76 (Rev. A)
Figure 1. Sychronous Data Timing
tSKHI
SK
tDIS
DI
tCSS
CS
tDIS
DO
tPD0,tPD1
DATA VALID
tCSMIN
VALID
VALID
tDIH
tSKLOW
tCSH
Figure 2. Read Instruction Timing
SK
CS
Don't Care
AN
DI
1
1
0
AN-1
A0
DO
HIGH-Z
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Figure 3. Write Instruction Timing
SK
tCSMIN
CS
AN
DI
1
0
1
tSV
DO
HIGH-Z
tEW
BUSY
READY
tHZ
HIGH-Z
AN-1
A0
DN
D0
STATUS
VERIFY
STANDBY
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1090 Rev. B
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
