TECHNICAL
MANUAL
8101/8104
Gigabit Ethernet
Controller
November 2001
®
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
Document DB14-000123-04, Fourth Edition (November 2001)
This document describes revision/release 1 of the LSI Logic Corporation
8101/8104 Gigabit Ethernet Controller and will remain the official reference
source for all revisions/releases of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved. Portions
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design is a registered trademark of LSI Logic Corporation. All
other brand and product names may be trademarks of their respective
companies.
IF
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html
ii
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the
8101/8104 Gigabit Ethernet Controller. It contains a complete functional
description and includes complete physical and electrical specifications
for the 8101/8104.
The 8104 is functionally the same as the 8101, except that the 8104 is
in a 208-pin Ball Grid Array (BGA) package and the 8101 is in a 208-pin
Plastic Quad Flat Pack (PQFP) package
Audience
This document assumes that you have some familiarity with application
specific integrated circuits and related support devices. The people who
benefit from this book are:
•
•
Engineers and managers who are evaluating the 8101/8104 Gigabit
Ethernet Controller for possible use in a system
Engineers who are designing the 8101/8104 Gigabit Ethernet
Controller into a system
Organization
This document has the following chapters:
•
Chapter 1,
Introduction,
describes the 8101/8104 Gigabit Ethernet
Controller, its basic features and benifits. This chapter also describes
the differences between the 8101 and 8104.
Chapter 2,
Functional Description,
provides a high level
description of the 8101/8104 Gigabit Ethernet Controller.
•
8101/8104 Gigabit Ethernet Controller
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
iii
•
Chapter 3,
Signal Descriptions,
provides a description of the
signals used and generated by the 8101/8104 Gigabit Ethernet
Controller.
Chapter 4,
Registers,
provides a description of the register
addresses and definitions.
Chapter 5,
Application Information,
provides application
considerations.
Chapter 6,
Specifications,
describes the specifications of the
8101/8104 Gigabit Ethernet Controller.
•
•
•
Abbreviations Used in This Manual
100BASE-FX
100BASE-TX
10BASE-T
4B5B
BGA
CLK
CRC
CRS
CSMA
CWRD
DA
ECL
EOF
ESD
FCS
FDX
FEF
FLP
FX
HDX
HIZ
I/G
IETF
IPG
IREF
L/T
LSB
100 Mbit/s Fiber Optic Ethernet
100 Mbit/s Twisted-Pair Ethernet
10 Mbit/s Twisted-Pair Ethernet
4-Bit 5-Bit
Ball Grid Array
Clock
Cyclic Redundancy Check
Carrier Sense
Carrier Sense Multiple Access
Codeword
Destination Address
Emitter-Coupled Logic
End of Frame
End of Stream Delimiter
Frame Check Sequence
Full-Duplex
Far End Fault
Fast Link Pulse
Fiber
Half-Duplex
High Impedance
Individual/Group
Internet Engineering Task Force
Interpacket Gap
Reference Current
Length and Type
Least Significant Bit
iv
Preface
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
MIB
MLT3
MSB
mV
NLP
NRZI
NRZ
OP
PCB
pF
PRE
R/LH
R/LHI
R/LL
R/LLI
R/LT
R/LTI
R/WSC
RFC
RJ-45
RMON
SA
SFD
SNMP
SOI
Split-32
SSD
STP
TP
µH
µP
UTP
Management Information Base
Multilevel Transmission (3 levels)
Most Significant Bit
millivolt
Normal Link Pulse
Nonreturn to Zero Inverted
Nonreturn to Zero
Opcode
Printed Circuit Board
picofarad
Preamble
Read Latched High
Read Latched High with Interrupt
Read Latched Low
Read Latched Low with Interrupt
Read Latched Transition
Read Latched Transition with Interrupt
Read/Write Self Clearing
Request for Comments
Registered Jack-45
Remote Monitoring
Start Address or Station Address
Start of Frame Delimiter
Simple Network Management Protocol
Start of Idle
Independent 32-bit input and output busses; one for
transmit and one for receive
Start of Stream Delimiter
Shielded Twisted Pair
Twisted Pair
microHenry
microprocessor
Unshielded Twisted Pair
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is
italicized.
Preface
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
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