32 Bit RISC Microcontroller
TX04 Series
TMPM462F15/F10FG
© 2014 TOSHIBA CORPORATION
All Rights Reserved
TMPM462F15/F10FG
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TMPM462F15/F10FG
General precautions on the use of Toshiba MCUs
This Page explains general precautions on the use of Toshiba MCUs.
Note that if there is a difference between the general precautions and the description in the body of the docu-
ment, the description in the body of document has higher priority.
1. The MCUs’ operation at power-on
At power-on, internal state of the MCUs is unstable. Therefore, state of the pins is undefined until re-
set operation is completed.
When a reset is performed by an external reset pin, pins of the MCUs that use the reset pin are unde-
fined until reset operation by the external pin is completed.
Also, when a reset is performed by the internal power-on reset, pins of the MCUs that use the internal
power-on reset are undefined until power supply voltage reaches the voltage at which power-on reset is val-
id.
2. Unused pins
Unused input/output ports of the MCUs are prohibited to use. The pins are high-impedance.
Generally, if MCUs operate while the high-impedance pins left open, electrostatic damage or latch-up
may occur in the internal LSI due to induced voltage influenced from external noise.
Toshiba recommend that each unused pin should be connected to the power supply pins or GND pins
via resistors.
3. Clock oscillation stability
A reset state must be released after the clock oscillation becomes stable. If the clock is changed to anoth-
er clock while the program is in progress, wait until the clock is stable.
TMPM462F15/F10FG
Introduction: Notes on the description of SFR (Special Function Register) under this specification
An SFR (Special Function Register) is a control register for periperal circuits (IP).
The SFR addressses of IPs are described in the chapter on memory map, and the details of SFR are given in
the chapter of each IP.
Definition of SFR used in this specification is in accordance with the following rules.
a.
SFR table of each IP as an example
・
SFR tables in each chapter of IP provides register names, addresses and brief descriptions.
・
All registers have a 32-bit unique address and the addresses of the registers are defined as follows,
with some exceptions: "Base address + (Unique) address"
Base Address = 0x0000_0000
Register name
Control register
SAMCR
Address(Base+)
0x0004
0x000C
Note:
SAMCR register address is 32 bits wide from the address 0x0000_0004 (Base Address(0x00000000) +
unique address (0x0004)).
The register shown above is an example for explanation purpose and not for demonstration purpose.
This register does not exist in this microcontroller.
Note:
b. SFR(register)
・
Each register basically consists of a 32-bit register (some exceptions).
・
The description of each register provides bits, bit symbols, types, initial values after reset and func-
tions.
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