D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
SN74LS290
DECADE COUNTER;
4-BIT BINARY COUNTER
The SN54/74LS290 and SN54/74LS293 are high-speed 4-bit
ripple type counters partitioned into two sections. Each counter has a
divide-by-two section and either a divide-by-five (LS290) or
divide-by-eight (LS293) section which are triggered by a
HIGH-to-LOW transition on the clock inputs. Each section can be
used separately or tied together (Q to CP)to form BCD, Bi-quinary, or
Modulo-16 counters. Both of the counters have a 2-input gated Master
Reset (Clear), and the LS290 also has a 2-input gated Master Set
(Preset 9).
•
Corner Power Pin Versions of the LS90 and LS93
•
Low Power Consumption . . . Typically 45 mW
•
High Count Rates . . . Typically 42 MHz
•
Choice of Counting Modes . . . BCD, Bi-Quinary, Binary
•
Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP
(TOP VIEW)
http://onsemi.com
DECADE COUNTER;
4-BIT BINARY COUNTER
LOW POWER
SCHOTTKY
V
CC
14
MR
13
MR
12
CP
1
11
CP
0
10
Q
0
9
Q
3
8
NOTE:
The Flatpak version
has the same pinouts (Connection
Diagram) as the Dual In-Line Pack-
age.
14
J SUFFIX
CERAMIC
CASE 632-08
1
LS290
14
N SUFFIX
PLASTIC
CASE 646-06
1
1
MS
V
CC
14
2
NC
MR
13
3
MS
MR
12
4
Q
2
CP
1
11
5
Q
1
CP
0
10
6
NC
Q
0
9
7
GND
Q
3
8
14
1
D SUFFIX
SOIC
CASE 751A-02
LS293
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
1
NC
2
NC
3
NC
4
Q
2
5
Q
1
6
NC
7
GND
PIN NAMES
CP
0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to
÷
2 Section.
Clock (Active LOW going edge) Input to
÷
5 Section (LS290).
Clock (Active LOW going edge) Input to
÷
8 Section (LS293).
Master Reset (Clear) Inputs
Master Set (Preset-9, LS290) Inputs
Output from
÷
2 Section (Notes b & c)
Outputs from
÷
5 &
÷
8 Sections (Note b)
LOADING
(Note a)
HIGH
0.05 U.L.
0.05 U.L.
0.05 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
1.5 U.L.
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
μA
HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges.
c) The Q
0
Outputs are guaranteed to drive the full fan-out plus the CP
1
Input of the device.
©
Semiconductor Components Industries, LLC, 2006
July, 2006
−
Rev. 6
1
Publication Order Number:
SN74LS290/D
SN74LS290
LOGIC SYMBOL
1 3
1 2
10
11
CP
0
MS
10
Q
0
Q
1
Q
2
Q
3
11
CP
0
CP
1
MR
1 2
9
5 4
8
12 13
9
5 4
8
Q
0
Q
1
Q
2
Q
3
Figure
1.
LS290
Figure
2.
LS293
CP
1
MR
1 2
12 13
V
CC
= PIN 14
GND = PIN 7
NC = PINS 2, 6
V
CC
= PIN 14
GND = PIN 7
NC = PINS 1, 2, 3, 6
LOGIC DIAGRAMS
MS
1
MS
2
1
3
LS290
CP
0
10
J
S
D
Q
J
Q
J
Q
R
S
D
Q
CP
C
D
Q
CP
KC Q
D
CP
KC Q
D
CP
SC Q
D
CP
1
MR
1
MR
2
11
12
9
13
5
4
8
V
CC
= PIN 14
GND = PIN 7
= PIN NUMBERS
Q
3
Q
0
Q
1
Q
2
LS293
10
J
Q
J
Q
J
Q
J
Q
CP
0
CP
K Q
C
D
CP
K Q
C
D
CP
K Q
C
D
CP
K Q
C
D
V
CC
= PIN 14
GND = PIN 7
CP
1
MR
1
MR
2
11
12
9
13
5
4
8
= PIN NUMBERS
Q
3
Q
0
Q
1
Q
2
http://onsemi.com
2
SN74LS290
FUNCTIONAL DESCRIPTION
The LS290 and LS293 are 4-bit ripple type Decade, and
4-Bit Binary counters respectively. Each device consists of
four master/ slave flip-flops which are internally connected to
provide a divide-by-two section and a divide-by-five (LS290)
or divide-by-eight (LS293) section. Each section has a
separate clock input which initiates state changes of the
counter on the HIGH-to-LOW clock transition. State changes
of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are
subject to decoding spikes and should not be used for clocks
or strobes. The Q
0
output of each device is designed and
specified to drive the rated fan-out plus the CP
1
input of the
device.
A gated AND asynchronous Master Reset (MR
1
⋅
MR
2
) is
provided on both counters which overrides the clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS
1
⋅
MS
2
) is provided on the LS290 which
overrides the clocks and the MR inputs and sets the outputs
to nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes:
LS290
A. BCD Decade (8421) Counter — the CP
1
input must be
externally connected to the Q
0
output. The CP
0
input
LS290 MODE SELECTION
RESET/SET INPUTS
MR
1
H
H
X
L
X
L
X
MR
2
H
H
X
X
L
X
L
MS
1
L
X
H
L
X
X
L
MS
2
X
L
H
X
L
L
X
Q
0
L
L
H
OUTPUTS
Q
1
L
L
L
Q
2
Q
3
L
L
H
L
L
L
Count
Count
Count
Count
receives the incoming count and a BCD count sequence
is produced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q
3
output must be externally connected to the CP
0
input. The
input count is then applied to the CP
1
input and a
divide-by-ten square wave is obtained at output Q
0
.
C. Divide-By-Two and Divide-By-Five Counter — No
external interconnections are required. The first flip-flop is
used as a binary element for the divide-by-two function
(CP
0
as the input and Q
0
as the output). The CP
1
input is
used to obtain binary divide-by-five operation at the Q
3
output.
LS293
A. 4-Bit Ripple Counter — The output Q
0
must be externally
connected to input CP
1
. The input count pulses are
applied to input CP
0
. Simultaneous division of 2, 4, 8, and
16 are performed at the Q
0
, Q
1
, Q
2
, and Q
3
outputs as
shown in the truth table.
B. 3-Bit Ripple Counter — The input count pulses are applied
to input CP
1
. Simultaneous frequency divisions of 2, 4,
and 8 are available at the Q
1
, Q
2,
and Q
3
outputs.
Independent use of the first flip-flop is available if the reset
function coincides with reset of the 3-bit ripple-through
counter.
LS290
BCD COUNT SEQUENCE
COUNT
0
1
2
3
4
5
6
7
8
9
OUTPUT
Q
0
L
H
L
H
L
H
L
H
L
H
Q
1
L
L
H
H
L
L
H
H
L
L
Q
2
L
L
L
L
H
H
H
H
L
L
Q
3
L
L
L
L
L
L
L
L
H
H
NOTE: Output Q
0
is connected to Input CP
1
for BCD count.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
http://onsemi.com
3
SN74LS290
LS293 MODE SELECTION
RESET INPUTS
MR
1
H
L
H
L
MR
2
H
H
L
L
Q
0
L
OUTPUTS
Q
1
L
Q
2
L
Count
Count
Count
Q
3
L
TRUTH TABLE
COUNT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OUTPUT
Q
0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Q
1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
Q
2
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
Q
3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Note: Output Q
0
connected to input CP
1
.
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
−55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
−0.4
4.0
8.0
Unit
V
°C
mA
mA
http://onsemi.com
4
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
