CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. To prevent damage to the input protection circuit, input signals should never be greater than V
DD
nor less than V
SS
. Input currents must
not exceed 10mA even when the power is off.
3. A connection must be provided at every input terminal. All unused inputs must be connected to V
DD
or V
SS
, whichever is appropriate.
Electrical Specifications
Values at -55
o
C, 25
o
C, 125
o
C Apply to D Package
Values at -40
o
C, 25
o
C, 85
o
C Apply to E Package
TEST
CONDITIONS
25
o
C
-55
o
C
-40
o
C
85
o
C
125
o
C
MIN
TYP
MAX
UNITS
PARAMETER
SYMBOL
V
O
(V)
V
DD
(V)
DC ELECTRICAL SPECIFICATIONS
Quiescent Device Current
I
DD
(Max)
-
-
-
Output Low (Sink) Current
I
OL
(Min)
0.5
5
0.5
10
Output High (Source) Cur-
rent
I
OH
(Min)
4.5
0
9.5
0
Output Voltage Low Level
V
OL
(Max)
-
-
Output Voltage High Level
V
OH
(Min)
-
-
Input Low Voltage
V
IL
(Max)
0.5, 4.5
1, 9
Input High Voltage
V
IH
(Min)
0.5, 4.5
1, 9
Input Current
I
IN
(Max)
-
5
10
15
5
5
10
10
5
5
10
10
5
10
5
10
5
10
5
10
-
-
-
-
100
1200
248
3000
-100
-1200
-248
-3000
0.15
0.15
4.85
9.85
1.5
3
3.6
7.1
-
-
-
-
96
1155
239
2868
-96
-1155
-239
-2868
0.15
0.15
4.85
9.85
1.5
3
3.6
7.1
-
-
-
-
66
787
164
1968
-66
-787
-164
-1968
0.15
0.15
4.85
9.85
1.4
2.9
3.5
7
-
-
-
-
56
672
140
1680
-56
-672
-140
-1680
0.15
0.15
4.85
9.85
1.4
2.9
3.5
7
-
0.5
1.5
3
80
960
200
2400
-80
-960
-200
-2400
-
-
4.85
9.85
-
-
3.5
7
-
0.75
2
4
160
1920
400
4800
-160
-1920
-400
-4800
-
-
-
-
2.25
4.5
2.25
4.5
10
1
2.5
5
-
-
-
-
-
-
-
-
0.15
0.15
-
-
1.5
3
-
-
-
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
pA
Refer to the CD4000B Series data book 250.5 for general operating and application considerations.
8-43
CD22402
Switching Electrical Specifications
T
A
= 25
o
C and C
L
= 15pF. Typical Temperature Coefficient for All Values of V
DD
= 0.3%/
o
C
TEST
CONDITIONS
PARAMETER
(NOTE 4)
Output State Propagation Delay Time (50% to 50%)
Low-to-High Level
High-to-Low Level
Output State Transition Time (10% to 90%)
Low-to-High
High-to-Low
Input Capacitance (Per Input)
NOTE:
4. The characteristics given are defined for unbuffered gate in the CMOS process of the CD22402.
t
TLH
t
THL
C
I
5
10
-
-
-
-
45
30
5
90
60
-
ns
ns
pF
t
PLH
t
PHL
5
10
-
-
40
20
80
40
ns
ns
SYMBOL
V
DD
(V)
MIN
TYP
MAX
UNITS
Logic Diagram
VERTICAL DRIVE (VERT. RESET
TO FIRST VERT. PULSE)
INTEGRATOR
10
+
R
S
Q
Q
GENLOCK OSC.
22
10K
10K
24
51pF
6
GENLOCK
SYNC
20
HOR.
DR
S
R
Q
Q
(NOTE 5)
21
1M
1N914
1
0.001µF
(NOTE 6)
23
1M
2
HOR. PROCESS
BLANKING
CLOCK TO
COUNTERS
CRYSTAL
32 TIMES
HORIZ.
503.496kHz
100pF
NOTES:
5. Pin 21 high when pin 20 is high (or open).
6. Pin 1 high inhibits clock.
FIGURE 1. DETAIL OF THE OSCILLATOR/GENLOCK PORTION OF THE CD22402
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