NCV7356
Advance Information
Single Wire CAN Transceiver
The NCV7356 is a physical layer device for a single wire data link
capable of operating with various Carrier Sense Multiple Access
with Collision Resolution (CSMA/CR) protocols such as the Bosch
Controller Area Network (CAN) version 2.0. This serial data link
network is intended for use in applications where high data rate is not
required and a lower data rate can achieve cost reductions in both the
physical media components and in the microprocessor and/or
dedicated logic devices which use the network.
The network shall be able to operate in either the normal data rate
mode or a high−speed data download mode for assembly line and
service data transfer operations. The high−speed mode is only
intended to be operational when the bus is attached to an off−board
service node. This node shall provide temporary bus electrical loads
which facilitate higher speed operation. Such temporary loads should
be removed when not performing download operations.
The bit rate for normal communications is typically 33 kbit/s, for
high−speed transmissions like described above a typical bit rate of
83 kbit/s is recommended. The NCV7356 is designed in accordance
to the Single Wire CAN Physical Layer Specification GMW3089
V2.3 and supports many additional features like undervoltage
lockout, timeout for faulty blocked input signals, output blanking
time in case of bus ringing and a very low sleep mode current.
Features
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MARKING
DIAGRAM
14
14
1
SO−14
D SUFFIX
CASE 751A
1
A
WL
Y
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
NCV7356
AWLYWW
PIN CONNECTIONS
GND 1
TxD 2
MODE0 3
MODE1 4
RxD
5
14 GND
13 NC
12 CANH
11 LOAD
10 V
BAT
9
8
(Top View)
INH
GND
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully Compatible with J2411 Single Wire CAN Specification
60
mA
(max) Sleep Mode Current
Operating Voltage Range 5.0 to 27 V
Up to 100 kbps High−Speed Transmission Mode
Up to 40 kbps Bus Speed
Selective BUS Wake−Up
Logic Inputs Compatible with 3.3 V and 5 V Supply Systems
Control Pin for External Voltage Regulators
Standby to Sleep Mode Timeout
Low RFI Due to Output Wave Shaping
Fully Integrated Receiver Filter
Bus Terminals Proof Against Short−Circuits and Transients
Loss of Ground Protection
Protection Against Load Dump, Jump Start
Thermal Overload and Short Circuit Protection
ESD Protection of 4.0 kV on CAN Pin (2.0 kV on Any Other Pin)
Undervoltage Lock Out
Bus Dominant Timeout Feature
NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
NC 6
GND 7
ORDERING INFORMATION
Device
NCV7356D
NCV7356DR2
Package
SOIC−14
SOIC−14
Shipping
†
55 Units / Rail
1000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
©
Semiconductor Components Industries, LLC, 2004
1
September, 2004 − Rev. P2
Publication Order Number:
NCV7356/D
NCV7356
V
BAT
INH
NCV7356
5 V Supply
and
References
Biasing and
V
BAT
Monitor
Reverse
Current
Protection
RC−Osc
Wave Shaping
CAN Driver
TxD
Time Out
CANH
Feedback
Loop
Input Filter
MODE0
LOAD
MODE
CONTROL
Receive
Comparator
Loss of
Ground
Detection
MODE1
RxD
RxD Blanking
Time Filter
Reverse
Current
Protection
GND
Figure 1. Block Diagram
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2
NCV7356
PACKAGE PIN DESCRIPTION
Pin
1, 7, 8, 14
2
3
4
5
6, 13
9
10
11
12
Symbol
GND
TXD
MODE0
MODE1
RXD
NC
INH
V
BAT
LOAD
CANH
Ground
Transmit data from microprocessor to CAN.
Operating mode select input 0.
Operating mode select input 1.
Receive data from CAN to microprocessor.
No Connection
Control pin for external voltage regulator (high voltage high side switch)
Battery input voltage.
Resistor load (loss of ground detection low side switch).
Single wire CAN bus pin.
Description
Functional Description
TxD Input Pin
Sleep Mode
TxD Polarity
•
TxD = logic 1 (or floating) on this pin produces an
undriven or recessive bus state (low bus voltage)
•
TxD = logic 0 on this pin produces either a bus normal
or a bus high voltage dominant state depending on the
transceiver mode state (high bus voltage)
If the TxD pin is driven to a logic low state while the sleep
mode (Mode 0 = 0 and Mode 1 = 0) is activated, the
transceiver can not drive the CANH pin to the dominant
state.
The transceiver provides an internal pull up current on
the TxD pin which will cause the transmitter to default to
the bus recessive state when TxD is not driven.
TxD input signals are standard CMOS logic levels.
Timeout Feature
Transceiver is in low power state, waiting for wake−up
via high voltage signal or by mode pins change to any state
other than 0,0. In this state, the CANH pin is not in the
dominant state regardless of the state of the TxD pin.
High−Speed Mode
This mode allows high−speed download with bitrates up
to 100 Kbit/s. The output waveshaping circuit is disabled
in this mode. Bus transmitter drive circuits for those nodes
which are required to communicate in high−speed mode
are able to drive reduced bus resistance in this mode.
High Voltage Wake−Up Mode
In case of a faulty blocked dominant TxD input signal,
the CANH output is switched off automatically after the
specified TxD timeout reaction time to prevent a dominant
bus.
The transmission is continued by next TxD L to H
transition without delay.
MODE0 and MODE1 Pins
This bus includes a selective node awake capability,
which allows normal communication to take place among
some nodes while leaving the other nodes in an undisturbed
sleep state. This is accomplished by controlling the signal
voltages such that all nodes must wake−up when they
receive a higher voltage message signal waveform. The
communication system communicates to the nodes
information as to which nodes are to stay operational
(awake) and which nodes are to put themselves into a non
communicating low power “sleep” state. Communication
at the lower, normal voltage levels shall not disturb the
sleeping nodes.
Normal Mode
The transceiver provides a weak internal pull down
current on each of these pins which causes the transceiver
to default to sleep mode when they are not driven. The
mode input signals are standard CMOS logic level for 3.3V
and 5V supply voltages.
MODE0
L
H
L
H
MODE1
L
L
H
H
Sleep Mode
High−Speed Mode
High Voltage Wake−Up
Normal Mode
Mode
Transmission bit rate in normal communication is
33 Kbits/s. In normal transmission mode the NCV7356
supports controlled waveform rise and overshoot times.
Waveform trailing edge control is required to assure that
high frequency components are minimized at the
beginning of the downward voltage slope. The remaining
fall time occurs after the bus is inactive with drivers off and
is determined by the RC time constant of the total bus load.
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NCV7356
RxD Output Pin
CAN BUS Input/Output Pin
Logic data as sensed on the single wire CAN bus.
RxD Polarity
•
RxD = logic 1 on this pin indicates a bus recessive
state (low bus voltage)
•
RxD = logic 0 on this pin indicates a bus normal or
high voltage bus dominant state
RxD in Sleep Mode
Wave Shaping in Normal and High Voltage Wake−Up
Mode
RxD does not pass signals to the microprocessor while in
sleep mode until a valid wake−up bus voltage level is
received or the MODE0 and MODE 1 pins are not 0, 0
respectively. When the valid wake−up bus voltage signal
awakens the transceiver, the RxD pin signals an interrupt
(logic 0). If there is no mode change within 250 ms (typ),
the transceiver re−enters the sleep mode.
When not in sleep mode all valid bus signals will be sent
out on the RxD pin.
RxD will be placed in the undriven or off state when in
sleep mode.
RxD Typical Load
Wave shaping is incorporated into the transmitter to
minimize EMI radiated emissions. An important
contributor to emissions is the rise and fall times during
output transitions at the “corners” of the voltage waveform.
The resultant waveform is one half of a sin wave of
frequency 50−65 kHz at the rising waveform edge and one
quarter of this sin wave at falling or trailing edge.
Wave Shaping in High−Speed Mode
Wave shaping control of the rising and falling waveform
edges are disabled during high−speed mode. EMI
emissions requirements are waived during this mode. The
waveform rise time in this mode is less than 1.0
ms.
Short Circuits
Resistance: 2.7 kW
Capacitance: < 25 pF
Bus LOAD Pin
Resistor ground connection with internal open−on−loss−
of−ground protection
If the CAN BUS pin is shorted to ground for any duration
of time, the current is limited as specified in the Electrical
Characteristics Table until an overtemperature shutdown
circuit disables the output high side drive source transistor
preventing damage to the IC.
Loss of Ground
When the ECU experiences a loss of ground condition,
this pin is switched to a high impedance state.
The ground connection through this pin is not interrupted
in any transceiver operating mode including the sleep
mode. The ground connection only is interrupted when
there is a valid loss of ground condition.
This pin provides the bus load resistor with a path to
ground which contributes less than 0.1 V to the bus offset
voltage when sinking the maximum current through one
load resistor.
The transceiver’s maximum bus leakage current
contribution to V
ol
from the LOAD pin when in a loss of
ground state is 50
mA
over all operating temperatures and
3.5 < V
BAT
< 27 V.
V
BAT
Input Pin
(Vehicle
Battery Voltage)
In case of a valid loss of ground condition, the LOAD pin
is switched into high impedance state. The CANH
transmission is continued until the undervoltage lock out
voltage threshold is detected.
Loss of Battery
In case of loss of battery (V
BAT
= 0 or open) the
transceiver does not disturb bus communication. The
maximum reverse current into the power supply system
(V
BAT
) doesn’t exceed 500
mA.
INH Pin
The transceiver is fully operational as described in the
Electrical Characteristics Table over the range 6.0 V <
V
BAT
< 18 V as measured between the GND pin and the
V
BAT
pin.
For 5.0 V < V
Bat
< 6.0 V the bus operates in normal mode
with reduced dominant output voltage and reduced
receiver input voltage. High voltage wakeup is not possible
(dominant output voltage is the same as in normal or
high−speed mode).
The transceiver operates in normal mode when 18 V >
V
Bat
> 27 V at 85°C for one minute.
For 0 < V
BAT
< 4.0 V, the bus is passive (not driven
dominant) and RxD is undriven (high), regardless of the
state of the TxD pin (undervoltage lockout).
The INH pin is a high−voltage highside switch used to
control the ECU’s regulated microcontroller power supply.
After power−on, the transceiver automatically enters an
intermediate standby mode, the INH output will go high
(up to V
BAT
) turning on the external voltage regulator. The
external regulator provides power to the ECU. If there is no
mode change within 250 ms (typ), the transceiver re−enters
the sleep mode and the INH output goes to logic 0
(floating).
When the transceiver has detected a valid wake−up
condition (bus HVWU traffic which exceeds the wake−up
filter time delay) the INH output will become high (up to
V
BAT
) again and the same procedure starts as described
after power−on. In case of a mode change into any active
mode, the sleep timer is stopped and INH stays high (up to
V
BAT
). If the transceiver enters the sleep mode, INH goes
to logic 0 (floating) after 250 ms (typ) when no wake−up
signal is present
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NCV7356
Electrical Specification
All voltages are referenced to ground (GND). Positive
currents flow into the IC. The maximum ratings given in
the table below are limiting values that do not lead to a
MAXIMUM RATINGS
Rating
Supply Voltage, Normal Operation
Short−T
erm Supply Voltage, Transient
Symbol
V
BAT
V
BAT.LD
Condition
−
Load Dump; t < 500 ms
Jump Start; t < 1.0 min
Transient Supply Voltage
Transient Supply Voltage
Transient Supply Voltage
CANH Voltage
V
BAT.TR1
V
BAT.TR2
V
BAT.TR3
V
CANH
ISO 7637/1 Pulse 1 (Note 1)
ISO 7637/1 Pulses 2 (Note 1)
ISO 7637/1 Pulses 3A, 3B
V
BAT
< 27 V
V
BAT
= 0 V
Transient Bus Voltage
Transient Bus Voltage
Transient Bus Voltage
DC Voltage on Pin LOAD
DC Voltage on Pins TxD, MODE1, MODE0, RxD
ESD Capability of CANH
ESD Capability of Any Other Pins
Maximum Latch−Up Free Current at Any Pin
Maximum Power Dissipation
Thermal Impedance
Storage Temperature
Junction Temperature
Lead Temperature Soldering
Reflow: (SMD styles only)
V
CANHTR1
V
CANHTR2
V
CANHTR3
V
LOAD
V
DC
V
ESDBUS
V
ESD
I
LATCH
P
tot
q
JA
T
STG
T
J
T
sld
At T
A
= 125°C
In Free Air
−
−
60 second maximum above 183°C
−5°C/+0°C allowable conditions
ISO 7637/1 Pulse 1 (Note 2)
ISO 7637/1 Pulses 2 (Note 2)
ISO 7637/1 Pulses 3A, 3B (Note 2)
Via RT > 2.0 kW
−
Human Body Model
Eq. to Discharge 100 pF with 1.5 kW
Human Body Model
Eq. to Discharge 100 pF with 1.5 kW
−
Min
−0.3
−
−
−50
−
−200
−20
−40
−50
−
−200
−40
−0.3
−4000
−2000
−500
−
−
−55
−40
−
40
−
100
200
40
7.0
4000
2000
500
>400
(Note 3)
<70
150
150
240 peak
V
V
V
V
V
V
V
mA
mW
°C/W
°C
°C
°C
Max
18
40
27
−
100
200
Unit
V
V
(peak)
V
V
V
V
V
permanent damage of the device but exceeding any of these
limits may do so. Long term exposure to limiting values
may affect the reliability of the device.
1. ISO 7637 test pulses are applied to V
BAT
via a reverse polarity diode and >1.0
mF
blocking capacitor.
2. ISO 7637 test pulses are applied to CANH via a coupling capacitance of 1.0 nF.
3. The application board shall be realized with a ground copper foil area > 150 mm
2
.
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