S E M I C O N D U C T O R
CD74HC373, CD74HCT373,
CD54HC573, CD74HC573,
CD74HCT573
High Speed CMOS Logic
Octal Transparent Latch, Three-State Output
Description
The Harris CD74HC373, CD74HCT373, CD54HC573,
CD74HC573, and CD74HCT573 are high speed Octal Trans-
parent Latches manufactured with silicon gate CMOS technol-
ogy. They possess the low power consumption of standard
CMOS integrated circuits, as well as the ability to drive 15
LSTTL devices. The CD74HCT373 and CD74HCT573 are
functionally as well as pin compatible with the standard
74LS373 and 74LS573.
The outputs are transparent to the inputs when the latch
enable (LE) is high. When the latch enable (LE) goes low the
data is latched. The output enable (OE) controls the three-
state outputs. When the output enable (OE) is high the
outputs are in the high impedance state. The latch operation
is independent to the state of the output enable. The 373 and
573 are identical in function and differ only in their pinout
arrangements.
November 1997
Features
• Common Latch Enable Control
• Common Three-State Output Enable Control
• Buffered Inputs
• Three-State Outputs
• Bus Line Driving Capacity
• Typical Propagation Delay = 12ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C (Data to Output for HC373)
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC573F
CD74HC373E
CD74HCT373E
CD74HC573E
CD74HCT573E
CD74HC373M
CD74HCT373M
CD74HC573M
CD74HCT573M
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number are available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
20 Ld CERDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld PDIP
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
20 Ld SOIC
PKG.
NO.
F20.3
F20.3
E20.3
E20.3
E20.3
M20.3
M20.3
M20.3
M20.3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1997
File Number
1679.1
1
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Pinout
CD74HC373, CD74HCT373
(PDIP, SOIC)
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
CD54HC573, CD74HC573, CD74HCT573
(PDIP, SOIC, CERDIP)
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Functional Block Diagrams
CD74HC373, CD74HCT373, CD74HC573, CD74HCT573
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
G
LE
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CD74HCT573
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
G
LE
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
D
G
O
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
TRUTH TABLE
OUTPUT ENABLE
L
L
L
L
H
LATCH ENABLE
H
H
L
L
X
DATA
H
L
l
h
X
OUTPUT
H
L
L
H
Z
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior
to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
2
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V.
. . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Thermal Resistance (Typical, Note 3).
. . . θ
JA
(
o
C/W)
θ
JA
(
o
C/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
125
N/A
CERDIP Package . . . . . . . . . . . . . . . .
85
24
SOIC Package . . . . . . . . . . . . . . . . . . .
120
N/A
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
I
I
I
CC
V
CC
or
GND
V
CC
or
GND
V
OL
V
IH
or
V
IL
V
OH
V
IH
or
V
IL
-0.02
-0.02
-0.02
-6
-7.8
0.02
0.02
0.02
6
7.8
-
0
2
4.5
6
4.5
6
2
4.5
6
4.5
6
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.26
0.26
±0.1
8
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1
80
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
160
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
SYMBOL
V
I
(V)
I
O
(mA) V
CC
(V)
MIN
25
o
C
TYP
MAX
-40
o
C TO 85
o
C
MIN
MAX
-55
o
C TO 125
o
C
MIN
MAX
UNITS
3
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Three-State Leakage
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Three-State Leakage
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
NOTE:
4. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
I
CC
-
V
CC
to
GND
V
CC
or
GND
V
IL
or
V
IH
V
CC
-2.1
V
OL
V
IH
or
V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or
V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
-
V
I
(V)
V
IL
or
V
IH
I
O
(mA) V
CC
(V)
V
O
=
V
CC
or
GND
6
MIN
-
25
o
C
TYP
-
MAX
±0.5
-40
o
C TO 85
o
C
MIN
-
MAX
±5
-55
o
C TO 125
o
C
MIN
-
MAX
±10
UNITS
µA
-6
-7.8
0.02
4.5
6
4.5
3.98
5.48
-
-
-
-
-
-
0.1
3.84
5.34
-
-
-
0.1
3.7
5.2
-
-
-
0.1
V
V
V
6
7.8
-
0
V
O
=
V
CC
or
GND
-
4.5
6
5.5
5.5
6
-
-
-
-
-
-
-
-
-
-
0.26
0.26
±0.1
8
±0.5
-
-
-
-
-
0.33
0.33
±1
80
±5
-
-
-
-
-
0.4
0.4
±1
160
±10
V
V
µA
µA
µA
∆I
CC
4.5 to
5.5
-
100
360
-
450
-
490
µA
HCT Input Loading Table
UNIT LOADS
INPUT
OE
Dn
LE
HCT373
1.5
0.4
0.6
HCT573
1.25
0.3
0.65
NOTE: Unit Load is
∆I
CC
limit specified in DC Electrical Specifica-
tions table, e.g., 360µA max at 25
o
C.
4
CD74HC373, CD74HCT373, CD54HC573, CD74HC573, CD74HCT573
Prerequisite For Switching Specifications
PARAMETER
HC TYPES
LE Pulse Width
t
W
-
2
4.5
6
Set-up Time Data to LE
t
SU
-
2
4.5
6
Hold Time, Data to LE
(573)
t
H
-
2
4.5
6
Hold Time, Data to LE
(373)
t
H
-
2
4.5
6
HCT TYPES
LE Pulse Width
Set-up Time Data to LE
Hold Time, Data to LE
t
w
t
w
t
H
Input t
r
, t
f
= 6ns
25
o
C
V
CC
(V)
TYP
MAX
-40
o
C TO 85
o
C
MAX
-55
o
C TO
125
o
C
MAX
UNITS
-
-
-
4.5
4.5
4.5
16
13
10
-
-
-
-
-
-
20
16
13
-
-
-
24
20
15
-
-
-
ns
ns
ns
80
16
14
50
10
9
40
8
7
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100
20
17
65
13
11
50
10
9
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
120
24
20
75
15
13
60
12
10
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
Switching Specifications
PARAMETER
HC TYPES
Propagation Delay,
Data to Qn
(HC/HCT373)
SYMBOL
TEST
CONDITIONS
t
PLH
, t
PHL
C
L
= 50pF
2
4.5
6
-
-
-
12
-
-
-
14
-
-
-
14
-
-
-
12
150
30
26
-
175
35
30
-
175
35
30
-
150
30
26
-
190
38
33
-
220
44
37
-
220
44
37
-
190
38
33
-
225
45
38
-
265
53
45
-
265
53
45
-
225
45
38
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
L
= 15pF
Propagation Delay,
Data to Qn
(HC/HCT573)
t
PLH,
t
PHL
C
L
= 50pF
5
2
4.5
6
C
L
= 15pF
Propagation Delay,
LE to Qn
t
PLH,
t
PHL
C
L
= 50pF
5
2
4.5
6
C
L
= 15pF
Output Enabling Time
t
PZL,
t
PZH
C
L
= 50pF
5
2
4.5
6
C
L
= 15pF
5
5
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