Freescale Semiconductor
Technical Data
Document Number: MC34972
Rev. 1.0, 9/2013
Multiple Switch Detection
Interface with Suppressed
Wake-up
The 34972 Multiple Switch Detection Interface with suppressed
wake-up is designed to detect the closing and opening of up to 22
switch contacts. The switch status, either open or closed, is transferred
to the microprocessor unit (MCU) through a serial peripheral interface
(SPI). The device also features a 22-to-1 analog multiplexer for reading
inputs as analog. The analog input signal is buffered and provided on
the AMUX output pin for the MCU to read.
The 34972 device has two modes of operation, Normal and Sleep.
Normal mode allows programming of the device and supplies switch
contacts with pull-up or pull-down current as it monitors switch change
of state. The Sleep mode provides low quiescent current, which makes
the 34972 ideal for industrial products requiring low sleep-state
currents. This device is powered by SMARTMOS technology.
Features
•
•
•
•
•
•
•
•
•
Designed to operate 5.5 V
V
PWR
26 V
Switch input voltage range -14 V to V
PWR
, 40 V Max
Interfaces directly to MPU using 3.3 V / 5.0 V SPI protocol
Selectable wake-up on change of state
Selectable wetting current (16 or 2.0 mA)
Eight programmable inputs (switches to supply or ground)
14 switch-to-ground inputs
Typical standby current - V
PWR =
100
A
and V
DD
= 20
A
Active interrupt (
INT
) on change-of-switch state
34972
MULTIPLE SWITCH
DETECTION INTERFACE
EW SUFFIX (Pb-FREE)
98ARH99137A
32-PIN SOICW
EK SUFFIX (Pb-FREE)
98ASA10556D
32-PIN SOICW EP
ORDERING INFORMATION
Device
MC34972ATEW/R2
MC34972ATEK/R2
Temperature
Range (T
A
)
-40 to 85 °C
Package
32 SOICW
32 SOICW EP
V
DD
V
PWR
SP0
SP1
V
PWR
SP7
34972
VPWR
VDD
WAKE
V
PWR
V
DD
POWER SUPPLY
LVI
ENABLE
SG0
SG1
SG12
SG13
SI
SCLK
CS
SO
INT
AMUX
GND
MOSI
SCLK
CS
MISO
INT
AN0
MCU
WATCHDOG
RESET
Figure 1. 34972 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2013. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V
V
PWR
V
PWR
16.0
mA
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
16.0
mA
To
+
2.0 4.0V
–
SPI
mA Ref
Comparator
5.0V
V
PWR
5.0 V
To
+
4.0 V
–
SPI
Ref
Comparator
WAKE
WAKE
Control
SP0
V
PWR
V
PWR
, V
DD
, 5.0 V
POR
Bandgap
Sleep PWR
VPWR
VDD
GND
2.0
mA
16.0
mA
To
+
2.0 4.0 V
–
SPI
mA Ref
Comparator
V
PWR
V
PWR
16.0
mA
2.0
mA
SP7
5.0 V
Oscillator
and
Clock Control
V
PWR
5.0 V
Temperature
Monitor and
Control
5.0 V
125 k
V
PWR
V
PWR
16.0
mA
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
V
PWR
V
PWR
16.0
mA
2.0
mA
2.0
mA
SG0
SPI Interface
and Control
V
DD
125 k
INT
INT
Control
V
DD
MUX Interface
40
A
CS
V
DD
SCLK
SI
SO
SG13
To
+
4.0 V
–
SPI
Ref
Comparator
+
V
DD
Analog Mux
Output
–
AMUX
Figure 2. 34972 Simplified Internal Block Diagram
34972
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
GND
SI
SCLK
CS
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VPWR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
Exposed Pad
EK Suffix
Only
EK Suffix
18
17
SO
VDD
AMUX
INT
SP7
SP6
SP5
SP4
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
GND
SI
SCLK
CS
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG5
SG6
VPWR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
EW Suffix
18
17
SO
VDD
AMUX
INT
SP7
SP6
SP5
SP4
SG7
SG8
SG9
SG10
SG11
SG12
SG13
WAKE
Figure 3. 34972 Pin Connections
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 9.
Table 1. 34972 Pin Definitions
Pin Number
1
2
3
4
5–8
25 – 28
9 – 15,
18 – 24
16
17
29
30
31
32
Pin Name
GND
SI
SCLK
CS
SP0 – 3
SP4 – 7
SG0 – 6,
SG13 – 7
VPWR
WAKE
INT
AMUX
VDD
SO
EP
Pin Function
Ground
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Output
Input
Output
Ground
Formal Name
Ground
SPI Slave In
Serial Clock
Chip Select
Programmable
Switches 0 – 7
Switch-to-Ground
Inputs 0 – 13
Supply Input
Wake-up
Interrupt
Definition
Ground for logic, analog, and switch to supply inputs.
SPI control data input pin from the MCU to the 34972.
SPI control clock input pin.
SPI control chip select input pin from the MCU to the 34972. Logic [0}
allows data to be transferred in.
Programmable switch-to-supply or switch-to-ground input pins.
Switch-to-ground input pins.
Voltage supply input pin. Pin requires external reverse voltage
protection.
Open drain wake-up output. Designed to control a power supply
enable pin.
Open-drain output to MCU. Used to indicate an input switch change of
state.
Analog Multiplex Output Analog multiplex output.
Voltage Drain Supply
SPI Slave Out
Exposed Pad
3.3 / 5.0 V supply. Sets SPI communication level for the SO driver.
Provides digital data from the 34972 to the MCU.
It is recommended that the exposed pad is terminated to GND (pin 1)
and system ground, however, the device will perform as specified with
the exposed pad unterminated (floating).
34972
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
ELECTRICAL RATINGS
VDD Supply Voltage
CS,
SI, SO, SCLK,
INT
, AMUX
(1)
Symbol
Value
Unit
V
DC
–
–
(1)
-0.3 to 7.0
-0.3 to 40
-0.3 to 50
-0.3 to 45
-14 to 40
6.0
±2000
±2000
±200
750
500
V
DC
V
DC
V
DC
V
DC
MHz
V
WAKE
(1)
VPWR Supply Voltage
VPWR Supply Voltage at -40
C
(1)
Switch Input Voltage Range
Frequency of SPI Operation (V
DD
= 5.0 V)
ESD Voltage
(3)
Human Body Model
(2)
Applies to all non-input pins
Machine Model
Charge Device Model
Corner Pins
Interior Pins
THERMAL RATINGS
Operating Temperature
Ambient
Junction
Storage Temperature
Power Dissipation (T
A
= 25
Thermal Resistance
Non-Exposed Pad
Junction to Ambient
Junction to Lead
Exposed Pad
Junction to Ambient
Junction to Exposed Pad
Peak Package Reflow Temperature During Reflow
(5), (6)
–
–
–
–
V
ESD
C
T
A
T
J
T
STG
- 40 to 85
- 40 to 150
- 55 to 150
1.7
C
W
C)
(4)
P
D
C/W
R
JA
R
JL
R
JA
R
JC
T
PPRT
74
25
71
1.2
Note 6
°C
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. ESD data available upon request.
3. ESD1 testing is performed in accordance with the Human Body model (C
ZAP
= 100 pF, R
ZAP
= 1500
),
and ESD2 testing is performed
in accordance with the Machine model (C
ZAP
= 200 pF, R
ZAP
= 0
).
4.
5.
6.
Maximum power dissipation at T
J
= 150
C junction temperature with no heat sink used.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
34972
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 3.1 V
V
DD
5.25 V, 8.0 V
V
PWR
16 V, -40
C
T
A
125
C,
unless otherwise
noted.
(7)
Where applicable, typical values reflect the parameter’s approximate average value with V
PWR
= 13 V, T
A
= 25
C.
Characteristic
POWER INPUT
Supply Voltage
Supply Voltage Range Quasi-functional
(8)
Fully Operational
Supply Voltage Range Quasi-functional
(8)
Supply Current
All Switches Open, Normal Mode, Tri-state Disabled
Sleep State Supply Current
Scan Timer = 64 ms, Switches Open
Logic Supply Voltage
Logic Supply Current
All Switches Open, Normal mode
Sleep State Logic Supply Current
Scan Timer = 64 ms, Switches Open
SWITCH INPUT
Pulse Wetting Current Switch-to-Supply (Current Sink)
Pulse Wetting Current Switch-to-Ground (Current Source)
Sustain Current Switch-to-Supply Input (Current Sink)
Sustain Current Switch-to-Ground Input (Current Source)
Sustain Current Matching Between Channels on Switch-to-Ground I/Os
I
SUS(MAX)
- I
SUS(MIN)
I
SUS(MIN)
X 100
I
OFFSET
V
OFFSET
-10
V
OL
–
V
OH
V
DD
-0.1
V
TH
V
IN
3.70
-14
–
4.0
–
–
4.3
40
V
V
10
30
V
2.5
10
mV
I
PULSE
I
PULSE
I
SUSTAIN
I
SUSTAIN
I
MATCH
–
2.0
5.0
12
12
1.8
1.8
15
16
2.0
2.0
18
18
2.3
2.2
mA
mA
mA
mA
%
I
DD
(
SS
)
–
10
20
V
DD
I
DD
–
0.25
0.5
A
I
PWR
(
SS
)
40
3.1
70
–
100
5.25
V
mA
V
PWR
(
QF
)
V
PWR
(
FO
)
V
PWR
(
QF
)
I
PWR
(
ON
)
–
2.0
4.0
A
5.5
8.0
26
–
–
–
8.0
26
38/40
mA
V
Symbol
Min
Typ
Max
Unit
Input Offset Current When Selected as Analog
Input Offset Voltage When Selected as Analog
V
(SP&SGINPUTS)
to AMUX Output
Analog Operational Amplifier Output Voltage
(9)
Sink 250
A
Analog Operational Amplifier Output Voltage
Source 250
A
Switch Detection Threshold
Switch Input Voltage Range
Notes
7. T
C
is the T
CASE
of the package
8.
9.
Device operational. Table parameters may be out of specification.
This parameter is guaranteed by design.
-2.0
1.4
2.0
A
mV
34972
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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