VIV0102THJ
®
C
S
US
C
NRTL
US
VTM
Transformer
TM
FEATURES
•
48 Vdc to 1.5 Vdc 50 A transformer
- Operating from standard 48 V or 24 V PRM
TM
regulators
•
High efficiency (>89%) reduces system power
consumption
•
High density (334 A/in
3
)
•
“Half Chip” V
•
I Chip package enables surface mount,
low impedance interconnect to system board
•
Contains built-in protection features:
-
-
-
-
-
Overvoltage Lockout
Overcurrent
Short Circuit
Over Temperature
Reverse Inrush Protection
•
Provides enable / disable control, internal temperature
monitoring, current monitoring
•
ZVS / ZCS resonant Sine Amplitude Converter topology
•
Less than 50ºC temperature rise at full load
in typical applications
TYPICAL APPLICATIONS
DESCRIPTION
The V
•
I Chip
TM
transformer is a high efficiency (>89%) Sine
Amplitude Converter
TM
(SAC
TM
) operating from a 26 to 55 Vdc
primary bus to deliver an isolated output. The Sine Amplitude
Converter offers a low AC impedance beyond the bandwidth of
most downstream regulators, which means that capacitance
normally at the load can be located at the input to the Sine
Amplitude Converter. Since the K factor of the VIV0102THJ is
1/32, that capacitance value can be reduced by a factor of
1024, resulting in savings of board area, materials and total
system cost.
The VIV0102THJ is provided in a V
•
I Chip package compatible
with standard pick-and-place and surface mount assembly
processes. The co-molded V
•
I Chip package provides enhanced
thermal management due to large thermal interface area and
superior thermal conductivity. With high conversion efficiency
the VIV0102THJ increases overall system efficiency and lowers
operating costs compared to conventional approaches.
The VIV0102THJ enables the utilization of Factorized Power
Architecture
TM
providing efficiency and size benefits by lowering
conversion and distribution losses and promoting high density
point of load conversion.
V
IN
= 26 to 55 V
V
OUT
= 0.8 to 1.7 V
(
NO LOAD
)
I
OUT
= 50 A
(
NOM
)
K= 1/32
•
High End Computing Systems
•
Automated Test Equipment
•
High Density Power Supplies
•
Communications Systems
•
0
PART NUMBER
VIV0102THJ
VIV0102MHJ
DESCRIPTION
-40°C to 125°C T
J
-55°C
TO
125°C T
J
Regulator
PR
PC
TM
IL
VC
SG
OS
CD
Voltage Transformer
PC
VC
IM
TM
PRM
+Out
+In
VTM
+Out
+In
V
IN
-In
-Out
-In
-Out
L
O
A
D
Factorized Power Architecture
(See Application Note AN:024)
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.9
02/2010
Page 1 of 16
VIV0102THJ
1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS
PRELIMINARY DATASHEET
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent
damage to the device.
MIN
MAX
UNIT
MIN
MAX
UNIT
+ IN to - IN
. . . . . . . . . . . . . . . . . . . . . . .
PC to - IN
. . . . . . . . . . . . . . . . . . . . . . . .
TM to -IN
. . . . . . . . . . . . . . . . . . . . . . . .
VC to - IN
. . . . . . . . . . . . . . . . . . . . . . . .
-1
-0.3
-0.3
-0.3
60
20
7
20
V
DC
V
DC
V
DC
V
DC
IM to - IN.................................................
+ IN / - IN to + OUT / - OUT (hipot)........
+ IN / - IN to + OUT / - OUT (working)...
+ OUT to - OUT.......................................
-1
0
3.15
2250
60
4
V
DC
V
DC
V
DC
V
DC
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted;
Boldface
specifications apply over the temperature
range of
-40°C < T
J
< 125°C (T-Grade);
All other specifications are at
T
J
= 25ºC
unless otherwise noted.
ATTRIBUTE
Input Voltage Range
V
IN
Slew Rate
V
IN
UV Turn Off
SYMBOL
V
IN
dV
IN
/dt
V
IN
_
UV
Module latched shutdown,
No external VC applied, I
OUT
= 50A
V
IN
= 42 V
V
IN
= 26 V to 55 V
V
IN
= 42 V, T
C
= 25ºC
V
IN
= 26 V to 55 V, T
C
= 25ºC
VC enable, V
IN
= 42 V C
OUT
= 5000 µF,
R
LOAD
= 28 mΩ
K = V
OUT
/ V
IN
, I
OUT
= 0 A
V
OUT
= V
IN
•
K - I
OUT
•
R
OUT
, Section 11
T
PEAK
< 10 ms, I
OUT
_
AVG
≤
50 A
I
OUT
_
AVG
≤
50 A
V
IN
= 42 V, I
OUT
= 50 A
V
IN
= 26 V to 55 V, I
OUT
= 50 A
V
IN
= 42 V, I
OUT
= 25 A
V
IN
= 42 V, T
C
= 100°C, I
OUT
= 50 A
10 A < I
OUT
< 50 A
T
C
= -40°C, I
OUT
= 50 A
T
C
= 25°C, I
OUT
= 50 A
T
C
= 100°C, I
OUT
= 50 A
16.2
1.2
2.6
CONDITIONS / NOTES
No external VC applied
VC applied
MIN
26
0
TYP
MAX
55
55
1
26
5
7.1
3.5
4.8
UNIT
V
DC
V/µs
V
No Load Power Dissipation
P
NL
W
Inrush Current Peak
DC Input Current
Transfer Ratio
Output Voltage
Output Current (Average)
Output Current (Peak)
Output Power (Average)
Efficiency (Ambient)
Efficiency (Hot)
Efficiency (Over Load Range)
Output Resistance (Cold)
Output Resistance (Ambient)
Output Resistance (Hot)
Switching Frequency
Output Ripple Frequency
Output Voltage Ripple
Output Inductance (Parasitic)
Output Capacitance (Internal)
Output Capacitance (External)
PROTECTION
OVLO
Overvoltage Lockout
Response Time
Output Overcurrent Trip
Short Circuit Protection Trip Current
Output Overcurrent Response
Time Constant
Short Circuit Protection Response Time
Thermal Shutdown Setpoint
I
INRP
I
IN
_
DC
K
V
OUT
I
OUT
_
AVG
I
OUT
_
PK
P
OUT
_
AVG
2.5
1/32
10
1.8
A
A
V/V
V
A
A
W
%
50
75
80
87.2
83.0
86.3
87.0
70.0
1.2
1.5
1.9
1.30
2.60
88.6
88.0
88.3
1.3
1.7
2.1
1.45
2.90
155
600
130
5000
1.5
1.9
2.3
1.60
3.20
300
η
AMB
η
HOT
η
20%
R
OUT
_
COLD
R
OUT
_
AMB
R
OUT
_
HOT
F
SW
F
SW
_
RP
V
OUT
_
PP
L
OUT
_
PAR
C
OUT
_
INT
C
OUT
_
EXT
%
%
mΩ
mΩ
mΩ
MHz
MHz
mV
pH
µF
µF
C
OUT
= 0 F, I
OUT
= 50 A, V
IN
= 42 V,
20 MHz BW, Section 12
Frequency up to 30 MHz,
Simulated J-lead model
V
OUT
= 1.5 V
VTM Standalone Operation
V
IN
pre-applied, VC enable
V
IN
_
OVLO
+
T
OVLO
I
OCP
I
SCP
T
OCP
T
SCP
T
J
_
OTP
Module latched shutdown
Effective internal RC filter
55.5
57.7
2.4
59.8
V
µs
60
75
Effective internal RC filter (Integrative).
From detection to cessation
of switching (Instantaneous)
125
75
8
1
130
100
A
A
ms
µs
135
ºC
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.9
02/2010
Page 2 of 16
VIV0102THJ
3.0 SIGNAL CHARACTERISTICS
PRELIMINARY DATASHEET
Specifications apply over all line and load conditions unless otherwise noted;
Boldface
specifications apply over the temperature
range of
-40°C < T
J
< 125°C (T-Grade);
All other specifications are at
T
J
= 25°C
unless otherwise noted.
VTM CONTROL : VC
• Used to wake up powertrain circuit.
• PRM VC can be used as valid wake-up signal source.
• A minimum of 12 V must be applied indefinitely for V
IN
< 26 V
• VC voltage may be continuously applied;
to ensure normal operation.
there will be minimal VC current drawn when V
IN
> 26 V and VC < 13.
• VC slew rate must be within range for a succesful start.
• Internal resistance used in adaptive loop compensation
SIGNAL TYPE
STATE
ATTRIBUTE
External VC Voltage
VC Current Draw Threshold
Steady
VC Current Draw
VC Internal Resistor
ANALOG
INPUT
Start Up
VC Slew Rate
VC Inrush Current
SYMBOL
V
VC
_
EXT
V
VC
_
TH
I
VC
R
VC
-
INT
dVC/dt
I
INR
_
VC
Required for proper startup;
0.02
CONDITIONS / NOTES
Required for startup, and operation
below 26 V. See Section 7.
Low VC current draw for V
IN
>26 V
VC = 13 V, V
IN
= 0 V
VC = 13 V, V
IN
> 26 V
VC = 16.5 V, V
IN
> 26 V
MIN
12
13
90
6
90
11
TYP
MAX UNIT
16.5
150
mA
kΩ
0.25
V/µs
mA
µs
µs
µF
V
V
VC = 16.5 V, dVC/dt = 0.25 V/µs
750
V
IN
pre-applied, PC floating, VC enable
VC Output Turn-On Delay
T
ON
500
C
PC
= 0 µF, C
OUT
= 5000 µF
Transitional
VC = 12 V to PC high, V
IN
= 0 V,
10
25
VC to PC Delay
T
VC
_
PC
dVC/dt = 0.25 V/µs
Internal VC Capacitance
C
VC
_
INT
VC = 0 V
2.2
PRIMARY CONTROL : PC
• The PC pin enables and disables the VTM.
• Module will shutdown when pulled low with an impedance
When held below 2 V, the VTM will be disabled.
less than 400
Ω.
• PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V
• In an array of VTMs, connect PC pin to synchronize startup.
during fault mode given V
IN
> 26 V and VC > 12 V.
• PC pin cannot sink current and will not disable other module
• After successful start-up and under no fault condition, PC can be used as
during fault mode.
a 5 V regulated voltage source with a 2 mA maximum current.
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX UNIT
V
mA
kΩ
µA
pF
kΩ
V
V
mA
µs
µs
PC Voltage
V
PC
4.7
5.0
5.3
PC Source Current
I
PC
_
OP
2
Steady
ANALOG
PC Resistance (Internal)
R
PC
_
INT
Internal pull down resistor
50
150
400
OUTPUT
PC Source Current
I
PC
_
EN
50
100
300
Start Up
PC Capacitance (Internal)
C
PC
_
INT
Section 7
50
PC Resistance (External)
R
PC
_
EXT
60
PC Voltage (Enable)
V
PC
_
EN
2
2.5
3
Enable
PC Voltage (Disable)
V
PC
_
DIS
2
Disable
DIGITAL
PC Pull Down Current
I
PC
_
PD
5.1
INPUT / OUPUT
PC Disable Time
T
PC
_
DIS
_
T
4
Transitional
PC Fault Response Time
T
FR
_
PC
From fault to PC = 2 V
100
TEMPERATURE MONITOR : TM
• The TM pin monitors the internal temperature of the VTM controller IC
• The TM pin has a room temperature setpoint of 3 V (@27°C)
within an accuracy of ±5°C.
and approximate gain of 10 mV/°C.
• Can be used as a "Power Good" flag to verify that the VTM is operating.
SIGNAL TYPE
STATE
ATTRIBUTE
TM Voltage
TM Source Current
TM Gain
TM Voltage Ripple
Disable
DIGITAL OUTPUT
(FAULT FLAG)
Transitional
TM Voltage
TM Resistance (Internal)
TM Capacitance (External)
TM Fault Response Time
SYMBOL
V
TM
_
AMB
I
TM
A
TM
V
TM
_
PP
V
TM
_
DIS
R
TM
_
INT
C
TM
_
EXT
T
FR
_
TM
CONDITIONS / NOTES
T
J
controller = 27°C
MIN
2.95
TYP
3.00
10
C
TM
= 0 F, V
IN
= 42 V,
I
OUT
= 50 A
Internal pull down resistor
From fault to TM = 1.5 V
25
120
0
40
10
200
50
50
MAX UNIT
3.05
100
V
µA
mV/°C
mV
V
kΩ
pF
µs
ANALOG
OUTPUT
Steady
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.9
02/2010
Page 3 of 16
VIV0102THJ
3.0 SIGNAL CHARACTERISTICS (CONT.)
PRELIMINARY DATASHEET
Specifications apply over all line and load conditions unless otherwise noted;
Boldface
specifications apply over the temperature
range of
-40°C < T
J
< 125°C (T-Grade);
All other specifications are at
T
J
= 25°C
unless otherwise noted.
CURRENT MONITOR : IM
• The nominal IM pin voltage varies between 0.39 V and 1.86 V
representing the output current within ±25% under all operating line
temperature conditions between 50% and 100%.
SIGNAL TYPE
STATE
ATTRIBUTE
IM Voltage (No Load)
IM Voltage (50%)
IM Voltage (Full Load)
IM Gain
IM Resistance (External)
SYMBOL
V
IM
_
NL
V
IM
_
50%
V
IM
_
FL
A
IM
R
IM
_
EXT
• The IM pin provides a DC analog voltage proportional to
the output current of the VTM.
CONDITIONS / NOTES
T
C
= 25ºC, V
IN
= 42 V, I
OUT
= 0 A
T
C
= 25ºC, V
IN
= 42 V, I
OUT
= 25 A
T
C
= 25ºC, V
IN
= 42 V, I
OUT
= 50 A
T
C
= 25ºC, V
IN
= 42 V, I
OUT
> 25 A
MIN
0.25
TYP
0.39
0.98
1.86
35.2
MAX
0.49
UNIT
V
V
V
mV/A
MΩ
ANALOG
OUTPUT
Steady
2.5
4.0 TIMING DIAGRAM
I
OUT
I
SSP
I
OCP
1
2 3
b
6
7
4
5
d
8
VC
V
VC-EXT
a
V
OVLO
V
IN
NL
≥ 26 V
c
e
f
V
OUT
TM
V
TM-AMB
PC
5V
3V
g
a: VC slew rate (dVC/dt)
b: Minimum VC pulse rate
c: T
OVLO
d: T
OCP
e: Output turn on delay (T
ON
)
f: PC disable time (T
PC-DIS
)
g: VC to PC delay (T
VC-PC
)
1. Initiated V
C
pulse
2. Controller start
3. V
IN
ramp up
4. V
IN
= V
OVLO
5. V
IN
ramp down no V
C
pulse
6. Overcurrent
7. Start up on short circuit
8. PC driven low
Notes:
– Timing and voltage is not to scale
– Error pulse width is load dependent
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.9
02/2010
Page 4 of 16
VIV0102THJ
5.0 APPLICATION CHARACTERISTICS
The following values, typical of an application environment, are collected at
T
C
= 25ºC
unless otherwise noted. See associated figures
for general trend data.
ATTRIBUTE
No Load Power Dissipation
Efficiency (Ambient)
Efficiency (Hot)
Output Resistance (Ambient)
Output Resistance (Hot)
Output Resistance (Cold)
Output Voltage Ripple
V
OUT
Transient (Positive)
V
OUT
Transient (Negative)
SYMBOL
P
NL
η
AMB
η
HOT
R
OUT
_
AMB
R
OUT
_
HOT
R
OUT
_
COLD
V
OUT
_
PP
V
OUT
_
TRAN
+
V
OUT
_
TRAN
-
CONDITIONS / NOTES
V
IN
= 42 V
V
IN
= 42 V, I
OUT
= 50 A
V
IN
= 42 V, I
OUT
= 50 A, T
C
= 100ºC
V
IN
= 42 V, I
OUT
= 50 A
V
IN
= 42 V, I
OUT
= 50 A, T
C
= 100ºC
V
IN
= 42 V, I
OUT
= 50 A, T
C
= -40ºC
C
OUT
= 0 F, I
OUT
= 50 A, V
IN
= 42 V,
20 MHz BW, Section 12
I
OUT
_
STEP
= 0 A
TO
50A, V
IN
= 42 V,
I
SLEW
> 10 A /us
I
OUT
_
STEP
= 50 A to 0 A, V
IN
= 42 V
I
SLEW
> 10 A /us
TYP
3.1
88.6
88.0
1.7
2.1
1.3
235
20
20
UNIT
W
%
%
mΩ
mΩ
mΩ
mV
mV
mV
No Load Power Dissipation vs. Line
7
6
5
4
3
2
1
26
29
32
36
39
42
45
49
52
55
92
Full Load Efficiency vs. Case Temperature
Full Load Efficiency (%)
90
88
86
84
82
80
-40
-20
0
20
40
60
80
100
Power Dissipation (W)
Input Voltage (V)
T
CASE
:
Case Temperature (°C)
100ºC
V
IN
:
26 V
42 V
55 V
-40ºC
25ºC
Figure 1 –
No load power dissipation vs. V
IN
Figure 2 –
Full load efficiency vs. temperature
Efficiency & Power Dissipation -40°C Case
90
85
80
20
92
Efficiency & Power Dissipation 25°C Case
18
16
14
12
10
18
Power Dissipation (W)
16
14
12
10
8
6
4
2
0
84
Efficiency (%)
Efficiency (%)
75
70
65
60
55
50
45
40
0
5
10
15
20
25
30
35
40
45
50
80
76
72
68
64
60
56
0
5
10
15
20
25
30
35
40
45
50
P
D
P
D
8
6
4
2
0
Output Current (A)
V
IN
:
26 V
42 V
55 V
26 V
42 V
55 V
V
IN
:
26 V
Output Current (A)
42 V
55 V
26 V
42 V
55 V
Figure 3 –
Efficiency and power dissipation at –40°C
Figure 4 –
Efficiency and power dissipation at 25°C
V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.9
02/2010
Page 5 of 16
Power Dissipation (W)
η
88
η
FPGA/CPLD
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