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LTC2289IUP#TR

产品描述Analog to Digital Converters - ADC LTC2289 - Dual 10-Bit, 80Msps Low Noise 3V ADC
产品类别模拟混合信号IC    转换器   
文件大小646KB,共24页
制造商ADI(亚德诺半导体)
官网地址https://www.analog.com
下载文档 详细参数 选型对比 全文预览

LTC2289IUP#TR概述

Analog to Digital Converters - ADC LTC2289 - Dual 10-Bit, 80Msps Low Noise 3V ADC

LTC2289IUP#TR规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称ADI(亚德诺半导体)
包装说明HVQCCN,
Reach Compliance Codenot_compliant
最大模拟输出电压1.9 V
最小模拟输出电压1 V
转换器类型D/A CONVERTER
输入位码OFFSET BINARY, 2\'S COMPLEMENT BINARY
输入格式PARALLEL
JESD-30 代码S-PQCC-N64
JESD-609代码e0
长度9 mm
最大线性误差 (EL)0.0586%
湿度敏感等级1
位数10
功能数量2
端子数量64
最高工作温度85 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码HVQCCN
封装形状SQUARE
封装形式CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度)235
认证状态Not Qualified
座面最大高度0.8 mm
标称安定时间 (tstl)0.0059 µs
标称供电电压3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn/Pb)
端子形式NO LEAD
端子节距0.5 mm
端子位置QUAD
处于峰值回流温度下的最长时间20
宽度9 mm

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LTC2289
Dual 10-Bit, 80Msps
Low Noise 3V ADC
FEATURES
DESCRIPTIO
Integrated Dual 10-Bit ADCs
Sample Rate: 80Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 422mW
61.6dB SNR at 70MHz Input
85dB SFDR at 70MHz Input
110dB Channel Isolation at 100MHz
Multiplexed or Separate Data Bus
Flexible Input: 1V
P-P
to 2V
P-P
Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2280 (10-Bit)
80Msps: LTC2294 (12-Bit), LTC2289 (10-Bit)
65Msps: LTC2293 (12-Bit), LTC2288 (10-Bit)
40Msps: LTC2292 (12-Bit), LTC2287 (10-Bit)
25Msps: LTC2291 (12-Bit), LTC2286 (10-Bit)
64-Pin (9mm
×
9mm) QFN Package
The LTC
®
2289 is a 10-bit 80Msps, low noise 3V dual A/D
converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2289 is perfect for
demanding imaging and communications applications
with AC performance that includes 61.6dB SNR and 85dB
SFDR for signals well beyond the Nyquist frequency.
DC specs include
±0.1LSB
INL (typ),
±0.1LSB
DNL (typ)
and
±0.6LSB
INL,
±0.5LSB
DNL over temperature. The
transition noise is a low 0.08LSB
RMS
.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIO S
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
TYPICAL APPLICATIO
+
ANALOG
INPUT A
INPUT
S/H
10-BIT
PIPELINED
ADC CORE
OV
DD
OUTPUT
DRIVERS
D9A
D0A
OGND
SNR (dBFS)
CLK A
CLOCK/DUTY CYCLE
CONTROL
MUX
CLOCK/DUTY CYCLE
CONTROL
OV
DD
CLK B
+
ANALOG
INPUT B
INPUT
S/H
10-BIT
PIPELINED
ADC CORE
OUTPUT
DRIVERS
D9B
D0B
OGND
2289 TA01
U
SNR vs Input Frequency,
–1dB, 2V Range, 80Msps
65
64
63
62
61
60
59
58
57
56
55
0
100
50
150
INPUT FREQUENCY (MHz)
200
2289 TA02
U
U
2289fa
1

LTC2289IUP#TR相似产品对比

LTC2289IUP#TR LTC2289IUP LTC2289CUP LTC2289IUP#TRPBF LTC2289CUP#TR LTC2289CUP#TRPBF LTC2289CUP#PBF LTC2289IUP#PBF
描述 Analog to Digital Converters - ADC LTC2289 - Dual 10-Bit, 80Msps Low Noise 3V ADC Analog to Digital Converters - ADC LTC2289 - Dual 10-Bit, 80Msps Low Noise 3V ADC Analog to Digital Converters - ADC LTC2289 - Dual 10-Bit, 80Msps Low Noise 3V ADC Analog to Digital Converters - ADC Dual 10-bit, 80Msps Low Power ADC 模数转换器 - ADC LTC2289 - Dual 10-Bit, 80Msps Low Noise 3V ADC 模数转换器 - ADC Dual 10-bit, 80Msps Low Power ADC 模数转换器 - ADC Dual 10-bit, 80Msps Low Power ADC 模数转换器 - ADC Dual 10-bit, 80Msps Low Power ADC
是否Rohs认证 不符合 不符合 不符合 符合 不符合 符合 符合 符合
包装说明 HVQCCN, 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64 9 X 9 MM, PLASTIC, MO-220WNJR-5, QFN-64 HVQCCN, HVQCCN, HVQCCN, HVQCCN, HVQCCN,
Reach Compliance Code not_compliant not_compliant not_compliant compliant not_compliant compliant compliant compliant
转换器类型 D/A CONVERTER ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD D/A CONVERTER D/A CONVERTER D/A CONVERTER D/A CONVERTER D/A CONVERTER
JESD-30 代码 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64 S-PQCC-N64
JESD-609代码 e0 e0 e0 e3 e0 e3 e3 e3
长度 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm
最大线性误差 (EL) 0.0586% 0.0586% 0.0586% 0.0586% 0.0586% 0.0586% 0.0586% 0.0586%
湿度敏感等级 1 1 1 1 1 1 1 1
位数 10 10 10 10 10 10 10 10
功能数量 2 1 1 2 2 2 2 2
端子数量 64 64 64 64 64 64 64 64
最高工作温度 85 °C 85 °C 70 °C 85 °C 70 °C 70 °C 70 °C 85 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 HVQCCN HVQCCN HVQCCN HVQCCN HVQCCN HVQCCN HVQCCN HVQCCN
封装形状 SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
封装形式 CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度) 235 235 235 260 235 260 260 260
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
标称供电电压 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V
表面贴装 YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL COMMERCIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Matte Tin (Sn) Tin/Lead (Sn/Pb) Matte Tin (Sn) MATTE TIN MATTE TIN
端子形式 NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD
端子节距 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm 0.5 mm
端子位置 QUAD QUAD QUAD QUAD QUAD QUAD QUAD QUAD
处于峰值回流温度下的最长时间 20 20 20 30 20 30 30 30
宽度 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm 9 mm
最大模拟输出电压 1.9 V - - 1.9 V 1.9 V 1.9 V 1.9 V 1.9 V
最小模拟输出电压 1 V - - 1 V 1 V 1 V 1 V 1 V
输入位码 OFFSET BINARY, 2\'S COMPLEMENT BINARY - - OFFSET BINARY, 2'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2'S COMPLEMENT BINARY OFFSET BINARY, 2'S COMPLEMENT BINARY OFFSET BINARY, 2'S COMPLEMENT BINARY
输入格式 PARALLEL - - PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
标称安定时间 (tstl) 0.0059 µs - - 0.0059 µs 0.0059 µs 0.0059 µs 0.0059 µs 0.0059 µs

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