S i 5 3 5 0 A- B
F
ACTORY
- P
ROGRAMMABLE
A
NY
- F
REQUENCY
CMOS
C
L O C K
G
ENERATOR
Features
www.silabs.com/custom-timing
Generates up to 8 non-integer-related
frequencies from 2.5 kHz to 200 MHz
Exact frequency synthesis at each
output (0 ppm error)
Glitchless frequency changes
Low output period jitter: < 70 ps pp, typ
Configurable Spread Spectrum
selectable at each output
User-configurable control pins:
Output Enable (OEB_0/1/2)
Power Down (PDN)
Frequency Select (FS_0/1)
Spread Spectrum Enable (SSEN)
Supports static phase offset
Rise/fall time control
Operates from a low-cost, fixed
frequency crystal: 25 or 27 MHz
Separate voltage supply pins provide
level translation:
Core VDD: 1.8 V, 2.5 V or 3.3 V
Output VDDO: 1.8 V, 2.5 V or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
(25 mA core, typ)
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compatible
Supports HCSL jitter compatible
swing
10-MSOP
20-QFN
Ordering Information:
See page 17
Applications
HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
Printers, scanners, projectors
Handheld instrumentation
Residential gateways
Networking/communication
Servers, storage
XO replacement
Description
The Si5350A is a highly-flexible, user-definable custom clock generator that is ideally
suited for replacing crystals and crystal oscillators in cost-sensitive applications.
Based on a PLL + high resolution fractional divider MultiSynth
TM
architecture, the
Si5350A can generate any frequency up to 200 MHz on each of its outputs with
0 ppm error. Spread spectrum is selectable (on/off) on any of the outputs. Custom
pin-controlled Si5350A devices can be requested using the ClockBuilder web-based
part number utility (www.silabs.com/ClockBuilder).
Functional Block Diagram
Si5350A (20-QFN)
XA
Si5350A (10-MSOP)
XA
OSC
XB
PLL
B
P0
P1
Control
Logic
MultiSynth 1
PLL
A
MultiSynth 0
VDDO
XB
OSC
PLL
A
MultiSynth
0
MultiSynth
1
VDDOA
CLK0
CLK1
VDDOB
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
CLK0
PLL
B
CLK1
P0
P1
Control
Logic
MultiSynth
2
MultiSynth
3
MultiSynth
4
MultiSynth
5
MultiSynth
6
MultiSynth
7
MultiSynth 2
CLK2
P2
P3
P4
Rev. 1.0 4/15
Copyright © 2015 by Silicon Laboratories
Si5350A-B
Si5350A-B
Table 1. The Complete Si5350/51 Clock Generator Family
Part Number
Si5351A-B-GT
Si5351A-B-GM
Si5351B-B-GM
Si5351C-B-GM
Si5351A-Bxxxxx-GT
Si5351A-Bxxxxx-GM
Si5351B-Bxxxxx-GM
Si5351C-Bxxxxx-GM
Si5350A-Bxxxxx-GT
Si5350A-Bxxxxx-GM
Si5350B-Bxxxxx-GT
Si5350B-Bxxxxx-GM
Si5350C-Bxxxxx-GT
Si5350C-Bxxxxx-GM
I2C or Pin
I2C
I2C
I2C
I2C
I2C
I2C
I2C
I2C
Pin
Pin
Pin
Pin
Pin
Pin
Frequency Reference
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL only
XTAL only
XTAL and/or Voltage
XTAL and/or Voltage
XTAL and/or CLKIN
XTAL and/or CLKIN
Programmed?
Blank
Blank
Blank
Blank
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Factory Pre-Programmed
Outputs
3
8
8
8
3
8
8
8
3
8
3
8
3
8
Datasheet
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5351-B
Si5350A-B
Si5350A-B
Si5350B-B
Si5350B-B
Si5350C-B
Si5350C-B
Notes:
1.
XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
2.
Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.
2
Rev. 1.0
Si5350A-B
T
ABLE O F
C
ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1. Si5350A Replaces Multiple Clocks and XOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4. Configuring the Si5350A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. Crystal Inputs (XA, XB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Output Clocks (CLK0–CLK7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3. Programmable Control Pins (P0–P4) Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2. 10-pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. 20-Pin QFN Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9. 10-pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
10. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
11. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
11.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Rev. 1.0
3
Si5350A-B
1. Electrical Specifications
Table 2. Recommended Operating Conditions
Parameter
Ambient Temperature
Core Supply Voltage
Symbol
T
A
V
DD
Test Condition
Min
–40
1.71
2.25
3.0
1.71
Output Buffer Voltage
V
DDOx
2.25
3.0
Typ
25
1.8
2.5
3.3
1.8
2.5
3.3
Max
85
1.89
2.75
3.60
1.89
2.75
3.60
Unit
°C
V
V
V
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD
and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all
VDDOx be powered up either before or at the same time as VDD.
Table 3. DC Characteristics
(V
DD
= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Core Supply Current*
Output Buffer Supply
Current (Per Output)*
Input Current
Symbol
I
DD
Test Condition
Enabled 3 outputs
Enabled 8 outputs
Power Down (PDN = VDD)
Min
—
—
—
—
—
—
—
Typ
20
25
—
2.2
—
—
50
Max
30
40
50
5.6
10
30
—
Unit
mA
mA
µA
mA
µA
µA
I
DDOx
I
P1-P4
I
P0
C
L
= 5 pF
Pins P1, P2, P3, P4
V
P1-P4
< 3.6 V
Pin P0
3.3 V VDDO, default high
drive.
Output Impedance
Z
OI
*Note:
Output clocks less than or equal to 100 MHz.
4
Rev. 1.0
Si5350A-B
Table 4. AC Characteristics
(V
DD
= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Powerup Time
Powerup Time, PLL Bypass Mode
Output Enable Time
Output Frequency Transition Time
Spread Spectrum Frequency
Deviation
Spread Spectrum Modulation Rate
Symbol
T
RDY
T
BYP
T
OE
T
FREQ
SS
DEV
SS
MOD
Test Condition
From V
DD
= V
DDmin
to valid output
clock, C
L
= 5 pF, f
CLKn
> 1 MHz
From V
DD
= V
DDmin
to valid output
clock, C
L
= 5 pF, f
CLKn
> 1 MHz
From OEB assertion to valid clock
output, C
L
= 5 pF, f
CLKn
> 1 MHz
f
CLKn
> 1 MHz
Down spread.
Selectable in 0.1% steps.
Min
—
—
—
—
–0.1
30
Typ
2
0.5
—
—
—
31.5
Max
10
1
10
10
–2.5
33
Unit
ms
ms
µs
µs
%
kHz
Table 5. Input Characteristics
(V
DD
= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Crystal Frequency
P0-P4 Input Low Voltage
P0-P4 Input High Voltage
Symbol
f
XTAL
V
IL_P0-4
V
IH_P0-4
Test Condition
Min
25
–0.1
Typ
—
—
—
—
Max
27
0.3 x V
DD
3.60
3.60
Unit
MHz
V
V
V
V
DD
= 2.5 V or 3.3 V
V
DD
= 1.8 V
0.7 x V
DD
0.8 x V
DD
Table 6. Output Characteristics
(V
DD
= 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Frequency Range
1
Load Capacitance
Duty Cycle
Rise/Fall Time
Output High Voltage
Output Low Voltage
Symbol
F
CLK
C
L
DC
t
r
/t
f
V
OH
V
OL
Test Condition
F
CLK
< 100 MHz
F
CLK
< 160 MHz, Measured at V
DD
/2
F
CLK
> 160 MHz, Measured at V
DD
/2
20%–80%, C
L
= 5 pF
Min
0.0025
—
45
40
—
V
DD
– 0.6
—
Typ
—
—
50
50
1
—
—
Max
200
15
55
60
1.5
—
0.6
Unit
MHz
pF
%
%
ns
V
V
Notes:
1.
Only two unique frequencies above 112.5 MHz can be simultaneously output.
2.
Measured over 10k cycles. Jitter is only specified at the default high drive strength (50
output impedance).
3.
Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20QFN package measured with clock outputs of 33.33, 74.25, 27,
24.576, 22.5792, 28.322, 125, and 48 MHz.
Rev. 1.0
5
FPGA/CPLD
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