SiHA24N65EF
www.vishay.com
Vishay Siliconix
E Series Power MOSFET with Fast Body Diode
D
FEATURES
• Fast body diode MOSFET using E series
technology
• Reduced t
rr
, Q
rr
, and I
RRM
• Low figure-of-merit (FOM) R
on
x Q
g
• Low input capacitance (C
iss
)
• Low switching losses due to reduced Q
rr
Available
• Ultra low gate charge (Q
g
)
• Avalanche energy rated (UIS)
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
Thin-Lead TO-220 FULLPAK
G
GD
S
S
N-Channel MOSFET
APPLICATIONS
PRODUCT SUMMARY
V
DS
(V) at T
J
max.
R
DS(on)
max. () at 25 °C
Q
g
max. (nC)
Q
gs
(nC)
Q
gd
(nC)
Configuration
V
GS
= 10 V
122
17
36
Single
700
0.156
• Telecommunications
- Server and telecom power supplies
• Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Consumer and computing
- ATX power supplies
• Industrial
- Welding
- Battery chargers
• Renewable energy
- Solar (PV inverters)
• Switch mode power supplies (SMPS)
• Applications using the following topologies
- LCC
- Phase shifted bridge (ZVS)
- 3-level inverter
- AC/DC bridge
ORDERING INFORMATION
Package
Lead (Pb)-free
Lead (Pb)-free and halogen-free
Thin-Lead TO-220 FULLPAK
SiHA24N65EF-E3
SiHA24N65EF-GE3
ABSOLUTE MAXIMUM RATINGS
(T
C
= 25 °C, unless otherwise noted)
PARAMETER
Drain-source voltage
Gate-source voltage
Continuous drain current (T
J
= 150 °C)
e
Pulsed drain
current
a
energy
b
V
GS
at 10 V
T
C
= 25 °C
T
C
= 100 °C
SYMBOL
V
DS
V
GS
I
D
I
DM
E
AS
P
D
T
J
, T
stg
T
J
= 125 °C
for 10 s
dV/dt
LIMIT
650
± 30
24
15
65
0.31
691
39
-55 to +150
70
50
300
0.6
W/°C
mJ
W
°C
V/ns
°C
Nm
A
UNIT
V
Linear derating factor
Single pulse avalanche
Maximum power dissipation
Operating junction and storage temperature range
Drain-source voltage slope
Reverse diode dV/dt
d
Soldering recommendations (peak temperature)
c
Mounting torque
M3 screw
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. V
DD
= 50 V, starting T
J
= 25 °C, L = 28.2 mH, R
g
= 25
,
I
AS
= 7 A
c. 1.6 mm from case
d. I
SD
I
D
, dI/dt = 900 A/μs, starting T
J
= 25 °C
e. Limited by maximum junction temperature
S18-0015-Rev. D, 15-Jan-18
Document Number: 91825
1
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
Vishay Siliconix
SYMBOL
R
thJA
R
thJC
TYP.
-
-
MAX.
65
3.2
UNIT
°C/W
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum junction-to-ambient
Maximum junction-to-case (drain)
SPECIFICATIONS
(T
J
= 25 °C, unless otherwise noted)
PARAMETER
Static
Drain-source breakdown voltage
V
DS
temperature coefficient
Gate-source threshold voltage (N)
Gate-source leakage
Zero gate voltage drain current
Drain-source on-state resistance
Forward transconductance
Dynamic
Input capacitance
Output capacitance
Reverse transfer capacitance
Effective output capacitance, energy
related
a
Effective output capacitance, time
related
b
Total gate charge
Gate-source charge
Gate-drain charge
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Gate input resistance
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
Pulsed diode forward current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
I
S
I
SM
V
SD
t
rr
Q
rr
I
RRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
SYMBOL
V
DS
V
DS
/T
J
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
fs
C
iss
C
oss
C
rss
C
o(er)
TEST CONDITIONS
V
GS
= 0 V, I
D
= 250 μA
Reference to 25 °C, I
D
= 1 mA
V
DS
= V
GS
, I
D
= 250 μA
V
GS
= ± 20 V
V
GS
= ± 30 V
V
DS
= 520 V, V
GS
= 0 V
V
DS
= 520 V, V
GS
= 0 V, T
J
= 125 °C
V
GS
= 10 V
I
D
= 12 A
V
DS
= 30 V, I
D
= 12 A
MIN.
650
-
2
-
-
-
-
-
-
-
-
-
-
TYP.
-
0.68
-
-
-
-
-
0.13
7.2
2774
128
4
96
333
81
17
36
24
34
80
46
0.5
MAX.
-
-
4
± 100
±1
1
500
0.156
-
-
-
-
UNIT
V
V/°C
V
nA
μA
μA
S
V
GS
= 0 V,
V
DS
= 100 V,
f = 1 MHz
pF
-
-
122
-
-
48
68
120
92
1.0
ns
nC
V
DS
= 0 V to 520 V, V
GS
= 0 V
C
o(tr)
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
R
g
f = 1 MHz, open drain
V
DD
= 520 V, I
D
= 12 A,
V
GS
= 10 V, R
g
= 9.1
V
GS
= 10 V
I
D
= 12 A, V
DS
= 520 V
-
-
-
-
-
-
-
-
0.2
-
-
-
-
-
-
-
-
0.9
151
0.9
13
24
A
65
1.2
288
2.1
-
V
ns
μC
A
G
S
T
J
= 25 °C, I
S
= 12 A, V
GS
= 0 V
T
J
= 25 °C, I
F
= I
S
= 12 A,
dI/dt = 100 A/μs, V
R
= 400 V
Notes
a. C
oss(er)
is a fixed capacitance that gives the same energy as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
b. C
oss(tr)
is a fixed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 % to 80 % V
DSS
S18-0015-Rev. D, 15-Jan-18
Document Number: 91825
2
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
TYPICAL CHARACTERISTICS
(25 °C, unless otherwise noted)
Vishay Siliconix
80
I
D
, Drain-to-Source Current (A)
R
DS(on)
, Drain-to-Source
On Resistance (Normalized)
60
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
T
J
= 25 °C
3
I
D
= 12 A
2.5
2
1.5
1
0.5
0
- 60 - 40 - 20 0
V
GS
= 10 V
40
20
6V
5V
0
0
5
10
15
20
25
30
20 40 60 80 100 120 140 160
V
DS
, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
T
J
, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
40
10 000
TOP 15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
T
J
= 150 °C
C
iss
I
D
, Drain-to-Source Current (A)
30
7V
Capacitance (pF)
1000
20
100
C
oss
V
GS
= 0 V, f = 1 MHz
C
iss
= C
gs
+ C
gd
, C
ds
shorted
C
rss
= C
gd
C
oss
= C
ds
+ C
gd
6V
10
5V
0
0
5
10
15
20
25
30
10
C
rss
1
0
100
200
300
400
500
600
V
DS
, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
V
DS
, Drain-to-Source Voltage (V)
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
80
16
5000
14
12
10
C
oss
(pF)
I
D
, Drain-to-Source Current (A)
60
40
T
J
= 150 °C
20
T
J
= 25 °C
V
DS
= 28.8 V
0
0
5
10
15
20
25
C
oss
500
E
oss
8
6
4
2
50
0
100
200
300
V
DS
400
500
600
0
V
GS
, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S18-0015-Rev. D, 15-Jan-18
Fig. 6 - C
oss
and E
oss
vs. V
DS
Document Number: 91825
3
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
E
oss
(μJ)
SiHA24N65EF
www.vishay.com
Vishay Siliconix
25
24
V
GS
,
Gate-to-Source
Voltage (V)
20
16
12
8
4
0
0
30
60
I
D
, Drain Current (A)
V
DS
= 520 V
V
DS
= 325 V
V
DS
= 130 V
20
15
10
5
0
90
120
150
25
50
75
100
125
150
Q
g
, Total
Gate
Charge (nC)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
T
J
, Case Temperature (°C)
Fig. 10 - Maximum Drain Current vs. Case Temperature
100
850
I
D
= 10 mA
825
T
J
= 150 °C
I
SD
, Reverse Drain Current (A)
V
DS
, Drain-to-Source
Breakdown Voltage (V)
1.4
1.6
800
775
750
725
700
675
650
- 60 - 40 - 20 0
10
T
J
= 25 °C
1
V
GS
= 0 V
0.1
0.2
0.4
0.6
0.8
1
1.2
20 40 60 80 100 120 140 160
V
SD
,
Source-Drain
Voltage (V)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Operation in this area
limited by R
DS(on)
T
J
, Junction Temperature (°C)
Fig. 11 - Temperature vs. Drain-to-Source Voltage
I
DM
limited
10
I
D
, Drain Current (A)
Limited by R
DS(on)
*
1
100 μs
1 ms
10 ms
T
C
= 25
°C
T
J
= 150 °C
Single
pulse
1
0.1
BVDSS limited
0.01
10
100
1000
V
DS
, Drain-to-Source Voltage (V)
* V
GS
> minimum V
GS
at which R
DS(on)
is
specified
Fig. 9 - Maximum Safe Operating Area
S18-0015-Rev. D, 15-Jan-18
Document Number: 91825
4
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
SiHA24N65EF
www.vishay.com
Vishay Siliconix
1
Duty cycle = 0.5
Normalized Effective Transient
Thermal Impedance
0.2
0.1
0.1
0.05
0.02
Single
pulse
0.01
0.0001
0.001
0.01
Pulse Time (s)
0.1
1
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
V
DS
V
GS
R
G
R
D
V
DS
t
p
V
DD
+
-
V
DD
D.U.T.
V
DS
10 V
Pulse width
≤
1 µs
Duty factor
≤
0.1 %
I
AS
Fig. 16 - Unclamped Inductive Waveforms
Fig. 13 - Switching Time Test Circuit
V
DS
90 %
10 V
Q
GS
10 %
V
GS
t
d(on)
t
r
t
d(off)
t
f
Q
G
Q
GD
V
G
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
L
Vary t
p
to obtain
required I
AS
R
G
V
DS
D.U.T
I
AS
+
-
12 V
0.2 µF
0.3 µF
V
DD
+
D.U.T.
10 V
t
p
0.01
Ω
V
GS
3 mA
-
V
DS
Fig. 15 - Unclamped Inductive Test Circuit
I
G
I
D
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
S18-0015-Rev. D, 15-Jan-18
Document Number: 91825
5
For technical questions, contact:
hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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