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SN74LS109A
Dual JK Positive
Edge−Triggered Flip−Flop
The SN74LS109A consists of two high speed completely
independent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform. The JK
design allows operation as a D flip-flop by simply connecting the J and
K pins together.
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LOW POWER SCHOTTKY
MODE SELECT
−
TRUTH TABLE
OPERATING MODE
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
*
INPUTS
S
D
L
H
L
H
H
H
H
C
D
H
L
L
H
H
H
H
J
X
X
X
h
l
h
l
K
X
X
X
h
h
l
l
OUTPUTS
Q
H
L
H
H
q
q
L
Q
L
H
H
L
q
q
H
16
1
Both outputs will be HIGH while both S
D
and C
D
are LOW, but the output
states are unpredictable if S
D
and C
D
go HIGH simultaneously.
PLASTIC
N SUFFIX
CASE 648
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
i, h (q) =
(or output) one set-up time prior to the LOW to HIGH clock transition.
16
1
SOIC
D SUFFIX
CASE 751B
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current
−
High
Output Current
−
Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
−0.4
8.0
Unit
V
°C
mA
mA
16
1
SOEIAJ
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
SN74LS109AN
SN74LS109AD
SN74LS109ADR2
SN74LS109AM
SN74LS109AMEL
Package
16 Pin DIP
SOIC−16
SOIC−16
SOEIAJ−16
SOEIAJ−16
Shipping
2000 Units/Box
38 Units/Rail
2500/Tape & Reel
See Note 1
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 8
1
Publication Order Number:
SN74LS109A/D
SN74LS109A
LOGIC DIAGRAM
SET (S
D
)
5(11)
CLEAR (C
D
)
1(15)
CLOCK
4(12)
Q
7(9)
Q
6(10)
J
2(14)
K
3(13)
LOGIC SYMBOL
5
2
4
3
J S
D
Q
CP
K C Q
D
1
V
CC
= PIN 16
GND = PIN 8
7
6
14
12
13
11
J S
D
Q
CP
K C Q
D
15
9
10
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
V
OL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
−0.65
3.5
0.25
0.35
0.4
0.5
20
40
0.1
0.2
−0.4
−0.8
−20
−100
8.0
Min
2.0
0.8
−1.5
Typ
Max
Unit
V
V
V
V
V
V
μA
mA
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
=
−
18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
I
OL
= 8.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
Output LOW Voltage
Input HIGH Current
J, K, Clock
Set, Clear
J, K, Clock
Set, Clear
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
I
IH
I
IL
I
OS
I
CC
Input LOW Current
J, K, Clock
Set, Clear
Output Short Circuit Current (Note 1)
Power Supply Current
mA
mA
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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2
SN74LS109A
AC CHARACTERISTICS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
f
MAX
t
PLH
t
PHL
Parameter
Maximum Clock Frequency
Clock, Clear, Set to Output
Min
25
Typ
33
13
25
25
40
Max
Unit
MHz
ns
ns
Test Conditions
V
CC
= 5.0 V
C
L
= 15 pF
AC SETUP REQUIREMENTS
(T
A
= 25°C, V
CC
= 5.0 V)
Limits
Symbol
t
W
t
s
t
h
Parameter
Clock High Clear, Set Pulse Width
Data Setup Time — HIGH
Data Setup Time —
LOW
Hold time
Min
25
20
20
5.0
Typ
Max
Unit
ns
ns
ns
ns
V
CC
= 5.0 V
Test Conditions
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3
SN74LS109A
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648−08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
_
10
_
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
_
10
_
0.51
1.01
−A−
16
9
B
1
8
F
S
C
L
−T−
H
K
G
D
16 PL
SEATING
PLANE
J
T A
M
M
0.25 (0.010)
M
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE J
−A−
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
_
7
_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
_
7
_
0.229
0.244
0.010
0.019
−B−
1
8
P
8 PL
0.25 (0.010)
M
B
S
G
F
K
C
−T−
SEATING
PLANE
R
X 45
_
M
D
16 PL
M
J
0.25 (0.010)
T B
S
A
S
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4
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