HD66740
HD66740
(112 x 80-dot Graphics LCD Controller/Driver)
Rev 1.0
August, 2001
Description
The HD66740, 112-by-80 dot-matrix graphics LCD controller and driver LSI, displays graphics such as
text, kanji and pictograms.
It can be configured to drive a dot-matrix liquid crystal under the control of the
microprocessor connected via the clock-synchronized serial or 4/8-bit bus. The HD66740 has a smooth
vertical scroll display and a double-height display for the remaining bit map areas. It fixed-displays a part
of the graphics icons so that the user can easily see a variety of information.
The HD66740 has various functions to reduce the power consumption of an LCD system such as low-
voltage operation of 1.8 V min., a booster to generate maximum five-times LCD drive voltage from the
supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleeder-
resistors.
Combining these hardware functions with software functions such as standby and sleep modes
The HD66740 is suitable for any portable battery-driven product requiring
allows fine power control.
long-term driving capabilities such as cellular phones, pagers, or electronic wallets.
Features
•
Control and drive of a graphics LCD
•
112 x 80-dot display
•
Fixed display of graphics icons (pictograms)
•
Low-power operation support:
Vcc = 1.8 to 3.6 V (low voltage)
V
LCD
= 4.5 to 15.0 V (liquid crystal drive voltage)
Triple, quadruple, or five-times booster for liquid crystal drive voltage
64-step contrast adjuster and voltage followers to decrease direct current flow in the LCD drive
bleeder-resistors
Power-save functions such as the standby mode and sleep mode supported
Programmable drive duty ratios and bias values displayed on LCD
High-speed clock-synchronized serial interface (serial transfer rate: 5 MHz max.)
I2C bus interface
High-speed 4-/8-bit bus interface capability
112-segment
×
80-common liquid crystal display driver
1,120-byte (112
×
80 dots) character generator RAM
•
•
•
•
•
1
HD66740
•
Vertical smooth scroll
Partial smooth scroll control (fixed display of graphics icons)
Vertical double-height display by each display line
Black-and-white reversed display
Wide range of instruction functions:
Display on/off control, black-and-white reversed
•
No wait time for instruction execution and RAM access
•
•
•
•
Internal oscillation and hardware reset
n-raster-row AC liquid-crystal drive (C-pattern waveform drive)
Shift change of segment and common driver
Tape carrier package (TCP)
Progammable Display Sizes and Duty Ratios
Graphics Display
Duty
Ratio
1/32
1/40
1/48
1/56
1/64
1/72
1/80
Optimum
Drive Bias
1/7
1/7
1/8
1/8
1/9
1/9.5
1/10
Bit Map
12 x 13-dot
Font Width
14 x 15-dot
Font Width
2 lines x 8
characters
2.5 lines x 8
characters
3 lines x 8
characters
3.5 lines x 8
characters
4 lines x 8
characters
4.5 lines x 8
characters
5 lines x 8
characters
16 x 16-dot
Font Width
2 lines x 7
characters
2.5 lines x 7
characters
3 line x 7
characters
3.5 lines x 7
characters
4 lines x 7
characters
4.5 lines x 7
characters
5 lines x 7
characters
•
•
•
•
Table 1
112 x 32 dots 2 lines x 9
characters
112 x 40 dots 3 lines x 9
characters
112 x 48 dots 3 lines x 9
characters
112 x 56 dots 4 lines x 9
characters
112 x 64 dots 5 lines x 9
characters
112 x 72 dots 6 lines x 9
characters
112 x 80 dots 6 lines x 9
characters
2
HD66740
<Target values>
Total Current Consumption Characteristics (Vcc = 3 V, TYP Conditions, LCD
Drive Power Current Included)
Total Power Consumption
Normal Display Operation
Character
Display Dot
Size
Duty
Ratio
R-C
Oscillation Frame
Frequency Frequency
75 kHz
75 kHz
75 kHz
75 kHz
75 kHz
80 kHz
90 kHz
73 Hz
73 Hz
74 Hz
74 Hz
73 Hz
70 Hz
70 Hz
Internal
Logic
(27 µA)
(27 µA)
(27 µA)
(27 µA)
(27 µA)
(32 µA)
(35 µA)
LCD
Power
(16 µA)
(16 µA)
(16 µA)
(16 µA)
(18 µA)
(18 µA)
(20 µA)
Sleep
Mode
Standby
Mode
Total*
Triple
(75 µA)
Triple
(75 µA)
Triple
(75 µA)
Triple
(75 µA)
112 x 32 dots 1/32
112 x 40 dots 1/40
112 x 48 dots 1/48
112 x 56 dots 1/56
112 x 64 dots 1/64
112 x 72 dots 1/72
112 x 80 dots 1/80
(15 µA) 0.1 µA
(15 µA)
(15 µA)
(15 µA)
Quadruple (15 µA)
(99 µA)
Quadruple (15 µA)
(104 µA)
Five-times (15 µA)
(135 µA)
Note : When a triple, quadruple, or five-times booster is used:
the total power consumption = Internal logic current + LCD power current x 3 (triple booster),
the total power consumption = Internal logic current + LCD power current x 4 (quadruple booster),
and
the total power consumption = Internal logic current + LCD power current x 5 (five-times booster)
Type Name
Types
HD66740TB0
HD66740WTB0
HCD66740BP
HCD66740WBP
External
Dimensions
Bending TCP
Bending TCP
Au-bumped chip
Au-bumped chip
Bus Interface
4/8-bits parallel and clock synchronized serial
4/8-bits parallel and I2C bus interface
4/8-bits parallel and clock synchronized serial
4/8-bits parallel and I2C bus interface
Operation Voltages
1.8 V to 3.6 V
3
HD66740
LCD Specification Comparison
(Under development)
Items
Character display sizes
Graphic display sizes
Multiplexing icons
Annunciator
Key scan control
LED control ports
General output ports
Operating power voltages
Liquid crystal drive voltages
I2C bus
Serial bus
Parallel bus
Expansion driver control
Liquid crystal drive duty ratios
Liquid crystal drive biases
Liquid crystal drive waveforms
Liquid crystal voltage booster
Bleeder-resistor for liquid crystal drive
Liquid crystal drive operational amplifier
Liquid crystal contrast adjuster
Horizontal smooth scroll
Vertical smooth scroll
Double-height display
DDRAM
CGROM
CGRAM
SEGRAM
No. of CGROM fonts
No. of CGRAM fonts
Font sizes
Bit map areas
R-C oscillation resistor/
oscillation frequency
Reset function
Low power control
HD66725
16 characters x 3 lines
96 x 26 dots
192
1/2 duty: 192
8 x4
—
3
1.8 V to 5.5 V
3 V to 6 V
—
Clock-synchronized serial
4 bits, 8 bits
Impossible
1/2, 10, 18, 26
1/4 to 1/6.5
B
Single, double, or triple
Incorporated (external)
Incorporated
Incorporated
3-dot unit
Line unit
Yes
80 x 8
20,736
384 x 8
96 x 8
240 + 192
64
6 x8
96 x 26
External resistor,
incorporated (32 kHz)
External
Partial display off
Oscillation off
Liquid crystal power off
Key wake-up interrupt
SEG, COM
—
—
TCP-170
—
Yes
170
10.97 x 2.51
80 µm
HD66728
16 characters x 10 lines
112 x 80 dots
—
—
8 x4
—
3
1.8 V to 5.5 V
4.5 V to 15 V
—
Clock-synchronized serial
4 bits, 8 bits
Impossible
HD66740
—
112 x 80 dots
—
—
—
—
—
1.8 V to 3.6 V
4.5 V to 15 V
I2C bus interface
(HD66740W)
Clock-synchronized serial
4 bits, 8 bits
Impossible
1/8, 16, 24, 32, 40, 48, 56, 64 1/8, 16, 24, 32, 40, 48, 56, 64
72, 80
72, 80
1/4 to 1/10
B, C
Triple, quadruple, or five-
times
Incorporated (external)
Incorporated
Incorporated
—
Line unit
Yes
160 x 8
20,736
1,120 x 8
—
240 + 192
64
6 x8
112 x 80
External resistor
(70–90 kHz)
External
Partial display off
Oscillation off
Liquid crystal power off
Key wake-up interrupt
SEG, COM
—
—
TCP-243
—
Yes
243
13.67 x 2.78
70 µm
1/4 to 1/10
B, C
Triple, quadruple, or five-
times
Incorporated (external)
Incorporated
Incorporated
—
Line unit
Yes
—
—
1,120 x 8
—
—
—
—
112 x 80
External resistor
(70–90 kHz)
External
Partial display off
Oscillation off
Liquid crystal power off
SEG, COM
—
—
TCP-233
—
Yes
243
9.40 x 2.18
50 µm
SEG/COM direction switching
QFP package
TQFP package
TCP package
Bare chip
Bumped chip
No. of pins
Chip sizes
Pad intervals
4
HD66740
HD66740 Block Diagram
OSC1
OSC2
RESET*
TEST
CPG
Timing generator
Instruction register
(IR)
Instruction
decoder
8
IM2-1
IM0/ID
CS*
RS
E/WR*/SCL
RW/RD*/SDA
DB0-DB7
System
interface
- Clock
synchro-
nized
serial
- I2C bus
- 4-bit bus
- 8-bit bus
Address
counter
(AC)
80-bit bidirectional
common shift register
Common
driver
COM1/80—
COM80/1
8
Data
register
(DR)
112-bit
112-bit Segment
SEG112/1
segment
latch
driver
shift
circuit
register
8
10
SEG1/112—
Character
generator RAM
(CGRAM)
1,120 bytes
Vci
8
C1+
C1-
C2+
C2-
C3+
C3-
C4+
C4-
VLOUT
Triple to
five-times
booster
LCD drive
voltage
selector
Parallel/serial converter
Contrast adjuster
Vcc
VTEST1—
VTEST3
VR
V
LCD
OPOFF
Drive bias controller
+ -
R
+ -
R
+ -
R
0
+ -
R
+ -
V1OUT
V2OUT
V3OUT
V4OUT
V5OUT
GND
5
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