Datasheet> 器件分类 > 半导体> 可编程逻辑器件> LCMXO3L-9400E-5BG256C

LCMXO3L-9400E-5BG256C: 产品描述FPGA - Field Programmable Gate Array MachXO3L; 9400 LUTs; 1.2V; 产品类别半导体可编程逻辑器件; 文件大小2MB，共91页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com; 标准

下载文档详细参数全文预览

LCMXO3L-9400E-5BG256C在线购买

供应商	器件名称	价格	最低购买	库存
	LCMXO3L-9400E-5BG256C	-	-	点击查看	点击购买

LCMXO3L-9400E-5BG256C概述

FPGA - Field Programmable Gate Array MachXO3L; 9400 LUTs; 1.2V

LCMXO3L-9400E-5BG256C规格参数

参数名称	属性值
Product Attribute	Attribute Value
制造商 Manufacturer	Lattice(莱迪斯)
产品种类 Product Category	FPGA - Field Programmable Gate Array
RoHS	Details
产品 Product	MachXO3L
Number of Logic Elements	9400
Number of Logic Array Blocks - LABs	1175
Number of I/Os	206 I/O
工作电源电压 Operating Supply Voltage	1.2 V
最小工作温度 Minimum Operating Temperature	0 C
最大工作温度 Maximum Operating Temperature	+ 85 C
安装风格 Mounting Style	SMD/SMT
封装 / 箱体 Package / Case	BGA-256
数据速率 Data Rate	900 Mb/s
Distributed RAM	73 kbit
Embedded Block RAM - EBR	432 kbit
Maximum Operating Frequency	400 MHz
工厂包装数量 Factory Pack Quantity	119

文档预览

下载PDF文档

全文
预览

MachXO3™ Family

Data Sheet

FPGA-DS-02032-2.1

March 2018

MachXO3™ Family

Data Sheet

Contents

Acronyms in This Document .................................................................................................................................................6

1. Introduction ..................................................................................................................................................................7

Features ...............................................................................................................................................................8

1.1.1. Solutions .........................................................................................................................................................8

1.1.2. Flexible Architecture .......................................................................................................................................8

1.1.3. Advanced Packaging .......................................................................................................................................8

1.1.4. Pre-Engineered Source Synchronous I/O ........................................................................................................8

1.1.5. High Performance, Flexible I/O Buffer ............................................................................................................8

1.1.6. Flexible On-Chip Clocking................................................................................................................................8

1.1.7. Non-volatile, Multi-time Programmable .........................................................................................................8

1.1.8. TransFR Reconfiguration .................................................................................................................................8

1.1.9. Enhanced System Level Support .....................................................................................................................8

1.1.10.

Applications ................................................................................................................................................8

1.1.11.

Low Cost Migration Path ............................................................................................................................8

2. Architecture ................................................................................................................................................................10

Architecture Overview ......................................................................................................................................10

PFU Blocks .........................................................................................................................................................12

2.2.1. Slices .............................................................................................................................................................12

2.2.2. Modes of Operation ......................................................................................................................................14

2.2.3. RAM Mode ....................................................................................................................................................14

2.2.4. ROM Mode ....................................................................................................................................................14

Routing ..............................................................................................................................................................15

Clock/Control Distribution Network...................................................................................................................15

2.4.1. sysCLOCK Phase Locked Loops (PLLs)............................................................................................................17

sysMEM Embedded Block RAM Memory ..........................................................................................................20

2.5.1. sysMEM Memory Block ................................................................................................................................20

2.5.2. Bus Size Matching .........................................................................................................................................20

2.5.3. RAM Initialization and ROM Operation ........................................................................................................20

2.5.4. Memory Cascading .......................................................................................................................................20

2.5.5. Single, Dual, Pseudo-Dual Port and FIFO Modes ..........................................................................................21

2.5.6. FIFO Configuration ........................................................................................................................................22

2.5.7. Memory Core Reset ......................................................................................................................................22

2.5.8. EBR Asynchronous Reset ..............................................................................................................................23

Programmable I/O Cells (PIC) ............................................................................................................................24

PIO .....................................................................................................................................................................26

2.7.1. Input Register Block ......................................................................................................................................26

2.7.2. Output Register Block ...................................................................................................................................26

2.7.3. Tri-state Register Block .................................................................................................................................27

Input Gearbox ...................................................................................................................................................27

Output Gearbox.................................................................................................................................................29

sysIO Buffer .......................................................................................................................................................31

2.10.1.

Typical I/O Behavior during Power-up......................................................................................................31

2.10.2.

Supported Standards ................................................................................................................................31

2.10.3.

sysIO Buffer Banks ....................................................................................................................................33

Hot Socketing ....................................................................................................................................................34

On-chip Oscillator ..............................................................................................................................................34

Embedded Hardened IP Functions ....................................................................................................................34

2.13.1.

Hardened I

C IP Core ................................................................................................................................35

2.13.2.

Hardened SPI IP Core ................................................................................................................................36

2.13.3.

Hardened Timer/Counter .........................................................................................................................38

User Flash Memory (UFM) ................................................................................................................................39

Standby Mode and Power Saving Options ........................................................................................................39

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-2.1

MachXO3™ Family

Data Sheet

Power On Reset ................................................................................................................................................. 40

Configuration and Testing ................................................................................................................................. 41

2.17.1.

IEEE 1149.1-Compliant Boundary Scan Testability ................................................................................... 41

2.17.2.

Device Configuration ................................................................................................................................ 41

TraceID .............................................................................................................................................................. 43

Density Shifting ................................................................................................................................................. 43

3. DC and Switching Characteristics ............................................................................................................................... 44

Absolute Maximum Rating ................................................................................................................................ 44

Recommended Operating Conditions ............................................................................................................... 44

Power Supply Ramp Rates ................................................................................................................................ 44

Power-On-Reset Voltage Levels ........................................................................................................................ 45

Hot Socketing Specifications ............................................................................................................................. 45

Programming/Erase Specifications ................................................................................................................... 45

ESD Performance .............................................................................................................................................. 46

DC Electrical Characteristics .............................................................................................................................. 46

Static Supply Current – C/E Devices .................................................................................................................. 47

Programming and Erase Supply Current – C/E Devices ..................................................................................... 48

sysIO Recommended Operating Conditions....................................................................................................... 49

sysIO Single-Ended DC Electrical Characteristics ............................................................................................... 50

sysIO Differential Electrical Characteristics ....................................................................................................... 51

3.13.1.

LVDS.......................................................................................................................................................... 51

3.13.2.

LVDS Emulation ........................................................................................................................................ 51

3.13.3.

BLVDS ....................................................................................................................................................... 52

3.13.4.

LVPECL....................................................................................................................................................... 53

3.13.5.

MIPI D-PHY Emulation .............................................................................................................................. 54

Typical Building Block Function Performance – C/E Devices

........................................................................... 57

3.14.1.

Pin-to-Pin Performance (LVCMOS25 12 mA Drive) .................................................................................. 57

3.14.2.

Register-to-Register Performance ............................................................................................................ 57

Derating Logic Timing ........................................................................................................................................ 57

Maximum sysIO Buffer Performance ................................................................................................................ 58

MachXO3L/LF External Switching Characteristics – C/E Devices ...................................................................... 59

sysCLOCK PLL Timing ......................................................................................................................................... 64

NVCM/Flash Download Time ............................................................................................................................ 66

JTAG Port Timing Specifications ........................................................................................................................ 66

sysCONFIG Port Timing Specifications .............................................................................................................. 68

C Port Timing Specifications ........................................................................................................................... 69

SPI Port Timing Specifications ........................................................................................................................... 69

Switching Test Conditions ................................................................................................................................. 69

4. Signal Descriptions...................................................................................................................................................... 70

Pin Information Summary ................................................................................................................................. 72

5. MachXO3 Part Number Description ........................................................................................................................... 77

6. Ordering Information ................................................................................................................................................. 78

MachXO3L Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging ...... 78

MachXO3LF Ultra Low Power Commercial and Industrial Grade Devices, Halogen Free (RoHS) Packaging .... 81

References .......................................................................................................................................................................... 85

Revision History .................................................................................................................................................................. 86

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-2.1

MachXO3™ Family

Data Sheet

Figures

Figure 2.1. Top View of the MachXO3L/LF-1300 Device ....................................................................................................10

Figure 2.2. Top View of the MachXO3L/LF-4300 Device ....................................................................................................11

Figure 2.3. PFU Block Diagram ............................................................................................................................................12

Figure 2.4. Slice Diagram ....................................................................................................................................................13

Figure 2.5. Primary Clocks for MachXO3L/F Devices ..........................................................................................................16

Figure 2.6. Secondary High Fanout Nets for MachXO3L/F Devices ....................................................................................17

Figure 2.7. PLL Diagram ......................................................................................................................................................18

Figure 2.8. sysMEM Memory Primitives .............................................................................................................................21

Figure 2.9. Memory Core Reset ..........................................................................................................................................23

Figure 2.10. EBR Asynchronous Reset (Including GSR) Timing Diagram .............................................................................23

Figure 2.11. Group of Four Programmable I/O Cells ..........................................................................................................25

Figure 2.12. Sentry Output Register Block Diagram (PIO on the Left, Top and Bottom Edges) ..........................................27

Figure 2.13. Input Gearbox .................................................................................................................................................28

Figure 2.14. Output Gearbox ..............................................................................................................................................30

Figure 2.15. MachXO3L/LF-1300 in 256 Ball Packages, MachXO3L/LF-2100, MachXO3L/LF-4300, MachXO3L/LF-6900 and

MachXO3L/LF-9400 Banks IO Banks ...................................................................................................................................33

Figure 2.16. MachXO3L/LF-640 and MachXO3L/LF-1300 Banks.........................................................................................33

Figure 2.17. Embedded Function Block Interface ...............................................................................................................35

Figure 2.18. I

C Core Block Diagram ...................................................................................................................................35

Figure 2.19. SPI Core Block Diagram ...................................................................................................................................37

Figure 2.20. Timer/Counter Block Diagram ........................................................................................................................38

Figure 3.1. LVDS Using External Resistors (LVDS25E) .........................................................................................................51

Figure 3.2. BLVDS Multi-point-Output Example .................................................................................................................52

Figure 3.3. Differential LVPECL ...........................................................................................................................................53

Figure 3.4. MIPI D-PHY Input Using External Resistors .......................................................................................................54

Figure 3.5. MIPI D-PHY Output Using External Resistors ....................................................................................................55

Figure 3.6.Receiver GDDR71_RX. Waveforms ....................................................................................................................64

Figure 3.7. Transmitter GDDR71_TX. Waveforms ..............................................................................................................64

Figure 3.8. JTAG Port Timing Waveforms ...........................................................................................................................67

Figure 3.9. Output Test Load, LVTTL and LVCMOS Standards ............................................................................................69

Tables

Table 1.1. MachXO3L/LF Family Selection Guide .................................................................................................................9

Table 2.1. Resources and Modes Available per Slice ..........................................................................................................12

Table 2.2. Slice Signal Descriptions .....................................................................................................................................13

Table 2.3. Number of Slices Required For Implementing Distributed RAM .......................................................................14

Table 2.4. PLL Signal Descriptions .......................................................................................................................................19

Table 2.5. sysMEM Block Configurations ............................................................................................................................20

Table 2.6. EBR Signal Descriptions ......................................................................................................................................21

Table 2.7. Programmable FIFO Flag Ranges ........................................................................................................................22

Table 2.8. PIO Signal List .....................................................................................................................................................26

Table 2.9. Input Gearbox Signal List ....................................................................................................................................27

Table 2.10. Output Gearbox Signal List ...............................................................................................................................29

Table 2.11. Supported Input Standards...............................................................................................................................32

Table 2.12. Supported Output Standards............................................................................................................................32

Table 2.13. Available MCLK Frequencies ............................................................................................................................34

Table 2.14. I

C Core Signal Description ...............................................................................................................................36

Table 2.15. SPI Core Signal Description ..............................................................................................................................37

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-2.1

MachXO3™ Family

Data Sheet

Table 2.16. Timer/Counter Signal Description .................................................................................................................... 39

Table 2.17. MachXO3L/LF Power Saving Features Description .......................................................................................... 40

Table 3.1. Absolute Maximum Rating

1,2,3

........................................................................................................................... 44

Table 3.2. Recommended Operating Conditions

.............................................................................................................. 44

Table 3.3. Power Supply Ramp Rates

................................................................................................................................ 44

Table 3.4. Power-On Reset Voltage Levels

1,2,3,4,5

................................................................................................................ 45

Table 3.5. Hot Socketing Specifications

1,2,3

......................................................................................................................... 45

Table 3.6. Programming/Erase Specifications .................................................................................................................... 45

Table 3.7. Static Supply Current – C/E Devices

1,2,3,6

............................................................................................................ 47

Table 3.8. Programming and Erase Supply Current – C/E Devices

1,2,3,4

.............................................................................. 48

Table 3.9. sysIO Recommended Operating Conditions ...................................................................................................... 49

Table 3.10. sysIO Single-Ended DC Electrical Charateristics

1,2

............................................................................................ 50

Table 3.11. LVDS25E DC Conditions.................................................................................................................................... 52

Table 3.12. BLVDS DC Condition

........................................................................................................................................ 53

Table 3.13. LVPECL DC Conditions ...................................................................................................................................... 54

Table 3.14. MIPI DC Conditions

......................................................................................................................................... 55

Table 3.15. MIPI D-PHY Output DC Conditions

.................................................................................................................. 56

Table 3.16. MachXO3L/LF External Switching Characteristics – C/E Devices

1,2,3,4,5,6,10

....................................................... 59

Table 3.17. NVCM/Flash Download Time

1,2,3

...................................................................................................................... 66

Table 3.18. sysCONFIG Port Timing Specifications ............................................................................................................. 68

Table 3.19. I

C Port Timing Specification

1,2

......................................................................................................................... 69

Table 3.20. SPI Port Timing Specifications .......................................................................................................................... 69

Table 3.21. Test Fixture Required Components, Non-Terminated Interfaces .................................................................... 69

Table 4.1. Signal Descriptions ............................................................................................................................................. 70

Table 4.2. MachXO3L/LF-9400C.......................................................................................................................................... 76

www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02032-2.1

推荐资源

JD642B设计共享: JD642B设计共享文件夹结构： l Documents文件夹下是项目相关的文档 l Hardware文件夹下是项目的硬件设计文件，其中包括PROTEL99SE版本和后来转换生成的 AD6.7版本，以及智能PDF文 ......; Aguilera 微控制器 MCU

Quartus2 时序设置基本参数描述: Quartus2 时序设置基本参数描述 fmax(最大时钟频率）：在不违反内部建立时间（tsu）和保持时间（th）要求下可以达到的最大时钟频率。模糊控制器 tsu（时钟建立时间）:在触发寄存器计时的时钟 ......; w842702 单片机

请打架帮我看一下此程序为什么温度数码管显示会乱跳？中断应该怎么改: /*----------------------------------------------- DS18b20数码管显示 ------------------------------------------------*/ #include //包含头文件，一般情况不需要改动，头文件包 ......; 18306934731 51单片机

51单片机例程资料（protues仿真+keil）: 这些程序楼主精心挑选的，都有protues仿真+keil 51单片机闪烁灯实验 http://shmily53.7958.com/download_9459295.html 51单片机流水灯实验 http://shmily53.7958.com/download_9459296.html ......; shmily53 51单片机

C语言算法之计算美女年龄: 先积累硬实力，再积累软实力，最后积累巧实力，而C语言是嵌入式技术的硬实力之一。学技术，重在日拱一卒、一点一滴的积累。今天一起分析C语言的算法练习之一，计算美女的年龄。 ......; XYD漫漫编程基础

急求cc2564的相关资料！！！: 各位，急求cc2564的相关资料！！！谢谢！ ...; 595361568 无线连接

英特尔为iPhone供应芯片重返手机市场

　　据台湾《经济日报》报道，苹果iPhone 3G下一代产品将采用英特尔Atom处理器，预计于2009、2010年上市。　　3G版iPhone将于7月11日在22个国家和地区同步上市，由于其极具竞争力的价格，甚至在某些国家是零元手机，因此受到了消费者的广泛关注，同时也使诺基亚、三星等手机大厂倍感压力。　　据悉，3G iPhone目前采用的是三星处理器核心，但因英特尔Atom处理器具有省电...[详细]
基于Nios II的多生理参数处理系统

　　随着医疗仪器设备向智能化、微型化、系列化、数字化和多功能方向的发展，医疗设备中逻辑控制器件也由采用中、小规模的集成芯片发展到应用现场可编程门阵列FPGA(Field Programmable Gate Array)。使用FPGA器件可以大大缩短医疗设备的研制周期，减少开发成本，同时还可以很方便地对设计进行在线修改，因此FPGA在医疗设备中有很广泛的应用。　　本文主要搭建一个多生理参数测...[详细]
高速CMOS图像传感器及发展趋势

　　传感器架构可由两分式、四分式或一个像素阵列组成。输出可为并行模拟输出，或一个10位数字输出或数字串行 LVDS输出。每个输出可高达每秒5,000万次的采样速度，这样就能实现每秒55亿像素的吞吐量。迄今为止，该图像传感器是具有最高连续像素吞吐量的一款。图像质量至少达到10位精度，因此摄像头数字化之后，数据吞吐量可为每秒55Gbit。这样高速的应用通常需要6个电晶体快照像素，且需要较高的灵敏度和...[详细]
英特尔下周一将发布迅驰2平台

　　随着笔记本电脑出货量开始超过台式电脑的出货量，每一次推出新的笔记本电脑平台对于英特尔来说都是非常重要的。英特尔将在7月14日星期一推出迅驰2平台，这个产品原来的代号是“Montevina”。由于英特尔自己为这个平台制作的集成的图形卡出现了问题，迅驰2平台的推出比英特尔原来的计划晚了几个星期。　　事实上，采用英特尔自己的集成的图形卡的迅驰2笔记本电脑在下周一还不能上市。下周一上市的只有配置...[详细]
减小ADC量化噪声的技术

　　数模转换器(ADC)提供了许多系统中模拟信号到数字信号的重要转换。它们完成一个模拟输入信号到二元有限长度输出命令的振幅量化，范围通常在6到18b之间，是一个固有的非线性过程。该非线性特性表现为ADC二元输出中的宽带噪声，称作量化噪声，它限制了一个ADC的动态范围。本文描述了两种时下最流行的方法来改善实际ADC应用中的量化噪声性能：过采样和高频抖动。　　为理解量化噪声缩减法，首先让我们回顾一...[详细]
改变血压监测仪的外观

　　“tensymetry”这个词在《韦伯斯特词典》中没有解释，但在医学界却广为人知。由Tensys Medical Systems公司开发的tensymetry是一种使用生物机械、电气、软件工程的专有组合技术。利用这三种强大的技术，你可在手术室内对病人的心跳血压进行精确、连续、实时和非侵入性测量。　　该技术结出的果实就是该公司的T-line Tensymeter产品。该产品线的最新进展是去年...[详细]
丁希仑：快乐“机器人”

　　“就好像变形金刚”，丁希仑这么描述他的机器人。　　当讲到飞船上的太阳帆板张开时，他的双臂直直地向两侧伸出，而讲到飞行器加速，他的胳膊贴紧两肋，好像那就是收拢的翅膀。提起机器人行走，他的上身微微扭动；有时，他会用一双结实的手转动一副不存在的旋柄。　　丁希仑，中国首屈一指的空间机器人专家，身高182，形色稳重，言语朴实，但介绍他的机器人时，动作丰富，常有笑容。　　丁教授声音温和，略带口音...[详细]
磁共振成像(MRI)

　　医疗成像正在取得显著进步。磁共振成像有助于检查患者体内的组织活动，可提供优质的软组织对比图像。ST提供从分立器件到32位数字处理器和存储器的广泛产品组合，帮助进一步加强磁共振成像应用。以下结构方块图可帮助您在众多推荐的适用产品中进行选择。 ...[详细]
血液分析仪

　　普通的血液分析仪具有的功能包括：平板显示、数据记录和主机通信。以下结构方块图可帮助您在众多推荐的适用产品中进行选择。 ...[详细]
召回植入医疗器械厂家要为患者出费用

　　《医疗器械召回管理办法》征求意见稿发布——记者从药监局了解到，关于《医疗器械召回管理办法》的征求意见稿已完成，其召回将根据安全隐患程度分为三级。　　同时，对于植入性医疗器械，生产企业要承担应召回或者更换该医疗器械而产生的费用。国家药监局表示，对征求意见稿中的内容有意见的企业、个人，可以在3月31日前将意见反馈至该局政策法规司法规处。 ...[详细]
英特尔面向嵌入式的双核处理器和高速芯片组

2008 年 7 月 15 日，英特尔公司推出面向嵌入式用户的英特尔 ® 酷睿™ 2 双核处理器 T9400 和移动式英特尔 ® GM45 高速芯片组，并提供长达 7 年的超长生命周期支持。本次推出的处理器和芯片组是全新英特尔 ® 迅驰 ® 2 平台的构成组件，可为移动应用程序带来更卓越的性能、更耐久的电池使用时间和广泛的无线网络互操作性。此外，今日推出的英特尔 ® 酷...[详细]
基于DSP的智能控制器高可靠性分析与设计(图)

　　硬件电路原理如图1所示，在具体设计中，每个部分都应考虑抗干扰问题，以最大限度地减小干扰对整个系统性能的影响，确保系统具有足够高的可靠性。　　　　图1 智能控制器硬件电路原理框图　　①DSP部分　　本控制器以TI公司的TMS320F2812（以下简称F2812）为核心，它是一款专用于控制的高性能、多功能、高性价比的32位定点DSP芯片。F2812部分的电路设计重点考虑如下问...[详细]
英特尔推出新的嵌入式新处理器及芯片组

　　英特尔推出了面向嵌入式用户的英特尔® 酷睿™2 双核处理器 T9400和移动式英特尔® GM45 高速芯片组，并提供长达7年的超长生命周期支持。本次推出的处理器和芯片组是全新的英特尔® 迅驰® 2 平台的构成组件，可为移动应用程序带来更耐久的电池使用时间和广泛的无线网络互操作性。　　新推出的英特尔® 酷睿™2 双核处理器 T9400经验证可支持英特尔® 5100 内存控制器中枢(MCH)...[详细]
TD-SCDMA射频测试解决方案

　　为确保中国TD-SCDMA网络规模商用的成功，运营商和设备供应商需要对入网设备进行大量的测试工作，其中射频测试尤为重要。安捷伦公司提供了符合3GPP 规范要求的TD-SCDMA 射频测试全面解决方案，并已广泛应用于各种基站、终端、直放站等设备测试中。下面将分别介绍应用于接收机测试、发射机测试（包括直放站测试）、射频一致性测试以及终端校准等方面的解决方案。 TD-SCDMA接收机性能...[详细]
游戏玩家失望：英特尔新款游戏芯片定价过高

　　英特尔公布了部分处理能力最强大的新款处理器价格，可能会令游戏玩家失望，因为它们的价格远高于媒体的报道。　　英特尔最新的价格表显示，英特尔面向游戏玩家的最新款处理器——Core 2 Extreme Quad-Core处理器的时钟频率为3.2GHz，价格为1499美元；与这款芯片略有不同的另一款芯片的价格为1399美元；另外一个版本Core 2 Extreme Quad-Core芯片的时钟频...[详细]

器件捷径: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多