FIN1108 • FIN1108T (Preliminary) LVDS 8 Port High Speed Repeater
March 2002
Revised May 2003
FIN1108 • FIN1108T (Preliminary)
LVDS 8 Port High Speed Repeater
General Description
This 8 port repeater is designed for high speed intercon-
nects utilizing Low Voltage Differential Signaling (LVDS)
technology.
The FIN1108 accepts and outputs LVDS levels with a typi-
cal differential output swing of 330 mV which provides low
EMI at ultra low power dissipation even at high frequen-
cies. The FIN1108 provides a V
BB
reference for AC cou-
pling on the inputs. In addition the FIN1108 can directly
accept LVPECL, HSTL, and SSTL-2 for translation to
LVDS.
The FIN1108T has internal termination across the receiver
inputs for reduced part count, reduced stub length and bet-
ter noise immunity. See Applications section.
Features
s
Greater than 800 Mbps data rate
s
3.3V power supply operation
s
3.5 ps maximum random jitter and 135 ps maximum
deterministic jitter
s
Wide rail-to-rail common mode range
s
LVDS receiver inputs accept LVPECL, HSTL, and
SSTL-2 directly
s
Ultra low power consumption
s
20 ps typical channel-to-channel skew
s
Power off protection
s
>
7.5 kV HBM ESD Protection
s
Meets or exceeds the TIA/EIA-644-A LVDS standard
s
Available in space saving 48-lead TSSOP package
s
Open circuit fail safe protection
s
V
BB
reference output
s
FIN1108T (R
T
) features Internal Termination Resistors
Ordering Code:
Order Number
FIN1108MTD
FIN1108TMTD
(Preliminary)
Package Number
MTD48
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
© 2003 Fairchild Semiconductor Corporation
DS500655
www.fairchildsemi.com
FIN1108 • FIN1108T (Preliminary)
Pin Descriptions
Pin Name
R
IN1+
, R
IN2+
,
R
IN3+
, R
IN4+
,
R
IN5+
, R
IN6+
,
R
IN7+
, R
IN8+
R
IN1−
, R
IN2−
,
R
IN3−
, R
IN4−
,
R
IN5−
, R
IN6−
,
R
IN7−
, R
IN8−
Description
Non-inverting LVDS Input
Connection Diagram
Inverting LVDS Input
D
OUT1+
, D
OUT2+
, Non-inverting Driver Output
D
OUT3+
, D
OUT4+
,
D
OUT5+
, D
OUT6+
,
D
OUT7+
, D
OUT8+
D
OUT1−
, D
OUT2−
, Inverting Driver Output
D
OUT3−
, D
OUT4−
,
D
OUT5−
, D
OUT6−
,
D
OUT7−
, D
OUT8−
EN
EN
12
EN
34
EN
56
EN
78
V
CC
GND
V
BB
Driver Enable Pin for All Output
Inverting Driver Enable Pin for
D
OUT1
and D
OUT2
Inverting Driver Enable Pin for
D
OUT3
and D
OUT4
Inverting Driver Enable Pin for
D
OUT5
and D
OUT6
Inverting Driver Enable Pin for
D
OUT7
and D
OUT8
Power Supply
Ground
Reference Voltage Output
Function Table
Inputs
EN
H
H
H
X
L
EN
xx
L
L
L
H
X
D
IN+
H
L
X
X
D
IN−
L
H
X
X
Outputs
D
OUT+
H
L
H
Z
Z
D
OUT−
L
H
L
Z
Z
Functional Diagram
Fail Safe Case
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don’t Care
Z
=
High Impedance
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2
FIN1108 • FIN1108T (Preliminary)
Applications
Signal Optimization via Internal Termination
For LVDS signaling in point-to-point applications, receivers
or repeaters with on-chip termination are preferable to
reduce the overshoot or undershoot due to the reflection
caused by stubs at receiver inputs. As a rule of thumb, usu-
ally the termination resistor for an LVDS receiver should be
placed as close as possible to the receiver, especially for
high speed applications. If the distance between termina-
tion resistors and receivers is too long, the interconnection
will be seen as an un-terminated stub which can produce
reflections resulting in higher EMI. Internal termination can
effectively smooth out this ringing which can otherwise
jeopardize the receiver noise margin. This is important for
reliable high-speed operation with tighter required signal
settling times. Below is a list of the advantages/disadvan-
tages of internal termination.
Internal termination is not suitable for all applications. In
order to set a proper V
OD
at the driver outputs, receivers
with on-chip termination resistors only work for point-to-
point applications since multi-drop applications would
require termination resistor for each receiver, reducing the
equivalent termination to R
T/n
. This would reduce the driver
output swing by n.
Advantages:
1. Reduced device count resulting in reduced board space
and production cost.
Disadvantages:
1. Without special process treatment, on-chip termination can
experience greater temperature variation. This is usually
tolerable for low speed applications that have a sufficient
unit interval.
2. For applications with high common-mode noise, a center
tapped capacitor at the receiver side is desirable to filter
out the common-mode voltage noise of the input LVDS sig-
nal. This scheme works for an external termination scheme
with two (50
Ω
each for nominal 100
Ω
termination resistor)
half-value termination resistors connected in series and
center tapped to a capacitor to Ground. To implement this
scheme using internal termination resistors, a center tap
pin would have to be used. This would increase the pack-
age size of the part.
2. Reduced reflections caused by the stub length on the
receiver inputs, improving the signal integrity.
3
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FIN1108 • FIN1108T (Preliminary)
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
LVDS DC Input Voltage (V
IN
)
LVDS DC Output Voltage (V
OUT
)
Driver Short Circuit Current (I
OSD
)
Storage Temperature Range (T
STG
)
Max Junction Temperature (T
J
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
260
°
C
7500V
400V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
Continuous 10 mA
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Magnitude of Differential
Voltage (|V
ID
|)
Common Mode Voltage
Range (V
IC
)
Operating Temperature (T
A
)
(0V
+
|V
ID
|/2) to (V
CC
−
|V
ID
|/2)
100 mV to V
CC
3.0V to 3.6V
−
65
°
C to
+
150
°
C
150
°
C
−
40
°
C to
+
85
°
C
Note 1:
The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Symbol
V
TH
V
TL
V
IH
V
IL
V
OD
∆V
OD
V
OS
∆V
OS
I
OS
Parameter
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input HIGH Voltage (EN or EN)
Input LOW Voltage (EN or EN)
Output Differential Voltage
V
OD
Magnitude Change from
Differential LOW-to-HIGH
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
Short Circuit Output Current
D
OUT
+
=
0V and D
OUT
−
=
0V,
Driver Enabled
V
OD
=
0V, Driver Enabled
I
IN
I
OFF
I
CCZ
I
CC
I
OZ
V
IC
C
IN
C
OUT
V
BB
R
T
Input Current (EN, EN, D
INx
+
, D
INx
−
) V
IN
=
0V to V
CC
, Other Input
=
V
CC
or 0V
(for Differential Inputs)
Power Off Input or Output Current
Disabled Power Supply Current
Power Supply Current
Disabled Output Leakage Current
Common Mode Voltage Range
Input Capacitance
Output Capacitance
Output Reference Voltage
Terminating Resistance
V
CC
=
3.3V, I
BB
=
0 to
−275 µA
1.125
Enable Input
LVDS Input
V
CC
=
0V, V
IN
or V
OUT
=
0V to 3.6V
Drivers Disabled
Drivers Enabled, Any Valid Input Condition
Driver Disabled, D
OUT
+
=
0V to 3.6V or
D
OUT
−
=
0V to 3.6V
V
ID
/2
3
3
3
1.2
100
1.375
−3.4
±3.4
R
L
=
100
Ω,
Driver Enabled,
See Figure 2
1.125
1.23
Test Conditions
See Figure 1; V
IC
= +0.05V, +
1.2V, or V
CC
−
0.05V
See Figure 1; V
IC
= +0.05V, +
1.2V, or V
CC
−
0.05V
−100
2.0
GND
250
330
V
CC
0.8
450
25
1.375
25
−6
±6
±20
±20
20
80
±20
V
CC
−
(V
ID
/2)
Min
Typ
(Note 2)
100
Max
Units
mV
mV
V
V
mV
mV
V
mV
mA
mA
µA
µA
mA
mA
µA
V
pF
pF
V
Ω
Note 2:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
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4
FIN1108 • FIN1108T (Preliminary)
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
SK(P)
t
SK(LH)
,
t
SK(HL)
t
SK(PP)
f
MAX
t
PZHD
t
PZLD
t
PHZD
t
PLZD
t
DJ
t
RJ
Parameter
Differential Output Propagation Delay
LOW-to-HIGH
Differential Output Propagation Delay
HIGH-to-LOW
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)(Note 7)
Differential Output Enable Time
from Z to HIGH
Differential Output Enable Time
from Z to LOW
Differential Output Disable Time
from HIGH to Z
Differential Output Disable Time
from LOW to Z
LVDS Data Jitter,
Deterministic
LVDS Clock Jitter,
Random (RMS)
V
ID
=
300 mV, PRBS
=
2
23
- 1,
V
IC
=
1.2V at 800 Mbps
V
ID
=
300 mV,
V
IC
=
1.2V at 400 MHz
R
L
=
100
Ω,
C
L
=
5 pF,
See Figure 2 and Figure 3
400
>630
3
3.1
2.2
2.5
80
1.9
5
5
5
5
135
3.5
R
L
=
100
Ω,
C
L
=
5 pF,
V
IC
=
V
ID
/2 to V
CC
−
(V
ID
/2),
Duty Cycle
=
50%,
See Figure 1 and Figure 1
Differential Output Rise Time (20% to 80%) V
ID
=
200 mV to 450 mV,
Test Conditions
Min
Typ
(Note 3)
0.75
0.75
0.29
0.29
1.1
1.1
0.4
0.4
0.02
0.02
0.02
1.75
1.75
0.58
0.58
0.2
0.15
0.5
Max
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ps
ps
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
Passing criteria for maximum frequency is the output V
OD
>
250 mV and the duty cycle is better than 45% / 55% with all channels switching.
Note 7:
Output loading is transmission line environment only; C
L
is
<
1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions
Note A: All LVDS input pulses have frequency
=
10 MHz, t
R
or t
F
< =
0.5 ns
Note B: C
L
includes all probe and jig capacitances
FIGURE 3. Differential Driver Propagation Delay
and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
5
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