NCP4060A
High Voltage Synchronous
Buck Converter
The NCP4060A is a high performance, high voltage, high
efficiency, fully integrated, voltage−mode synchronous buck
converter with constant frequency voltage mode control with input
feedforward architecture. It operates from input voltages ranging from
16 V to 80 V and it is capable of generating output voltages down to
1.25 V at 6 A DC loads and up to 10 A peak load currents, across a
wide range of ambient temperatures. The NCP4060A exhibits
protection features that protect the load from faults like over−voltage,
over−current and over−temperature. The NCP4060A adopts a
±1%
accurate reference voltage to maintain a tight−regulated output
voltage. It has a programmable switching frequency that can be set
from 100 to 500 kHz.
Features
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QFN19
CASE 485FL
1
MARKING DIAGRAM
•
Wide Input Voltage Range from 16 V to 80 V
•
Output Current Handling: 6 A
•
1.25 V Internal Reference Voltage Accurate to within
±1%
over the
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Entire Temperature Range
Programmable Switching Frequency from 100 to 500 kHz
Externally Programmable Soft−start
Auxiliary Bootstrap LDO from Output to Reduce Powerloss
External Error Amplifier Compensation
Lossless High−side and Low−side FET Current Sensing
Over−current Protection
Voltage Mode Control with Input Voltage Feed−forward
Power Good Output
Programmable VIN UVLO
Supports Prebias Start−ups
Over and Under−voltage Protection
Internal Over−temperature Protection
Hiccup Mode Operation for All Faults
19 Pin 6 mm x 6 mm QFN Package
A
WL
YY
WW
G
NCP4060A
AWLYYWWG
= Assembly Lot
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NCP4060AMNTXG
Package
QFN19
(Pb−Free)
Shipping
†
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Typical Application
•
Remote Radio Unit (RRU)
•
Telecom and Datacom Applications
•
High Voltage Point of Load
©
Semiconductor Components Industries, LLC, 2016
1
August, 2018 − Rev. 2
Publication Order Number:
NCP4060A/D
NCP4060A
VEXT
VB
VCC
VDD
VDD
RT
COMP
VDD
VREF +
E/A
−
OSC
Control Logic
Ramp Generator
PWM Logic
− and −
VSW
c
BST
VIN
LDO
VCC
VDD
VB
FB
SS
Soft Start
VCC
2
mA
VDD
Enable
Logic
1.2 V
POR
UVLO
Power Good
OCP, TSD
Protection
VB
EN
PG
PGND
ISET
AGND
Figure 1. Internal Block Diagram
VDD
VIN
VIN
EN
VOUT
VEXT
VDD
NCP4060A
BST
VOUT
VSW
PG
VCC
VB
RT
FB
COMP
ISET
SS
PGND
AGND
Figure 2. Typical Application Circuit
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2
NCP4060A
PIN CONNECTIONS
Table 1. PIN DESCRIPTION
Pin No.
1
2
3−4
5
6
7
8
9
10
11
12
13
Symbol
NC
BST
VSW
PGND
VIN
AGND
RT
ISET
SS
FB
COMP
EN
No Connect
High−side MOSFET driver input supply, a bootstrap capacitor connection between the switch node and this pin
The VSW pin is connected to the drain of the low−side MOSFET and the source of the high−side MOSFET.
Power ground reference
The VIN pin is connected to the drain of high−side MOSFET. Decouple this pin to PGND by placing decou-
pling capacitors close to the IC
Analog ground
A resistor from RT to AGND sets the switching frequency
A resistor from ISET pin to AGND sets the over−current protection (OCP) threshold
A capacitor from SS pin to AGND allows the user to adjust the soft−start ramp time
Connect FB to the center tap of external resistor divider to set the output voltage
Error Amplifier Output
When used as EN pin, float or drive this pin to > 1.2 V to enable the part; pull to ground to disable; for standby
mode, drive this pin to a voltage between 0.8 V & 1 V.
To implement VIN UVLO, and set the input voltage at which the part turns on, add a resistor divider from VIN
to PGND, and connect the center−tap to EN.
Power good indicator of the output voltage. Open−drain output. Connect PG to VDD with an external resistor
Analog input bias voltage. Connect to VB. Connect a 4.7
mF
ceramic capacitor from VDD to AGND
5.25 V LDO output and MOSFETs driver supply pin for NCP4060A. Bypass VB by 4.7
mF
ceramic capacitor to
AGND.
Output voltage is connected to this pin to enable LDO switch−over scheme to reduce power consumption. If
LDO switch−over scheme is not needed, tie VEXT to AGND.
No Connect
VCC input voltage for the LDO. Connect to VIN.
Description
14
15
16
17
18
19
PG
VDD
VB
VEXT
NC
VCC
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3
NCP4060A
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Power Supply to PGND
V
SW
to PGND
DC
Repetitive pulse < 100 ns
BST to SW
VEXT to PGND
All other pins
AGND to PGND
Electrostatic Discharge Human body model
Electrostatic Discharge Charge device model
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
AGND, PGND
HBM
CDM
T
A
T
J
T
J(MAX)
T
stg
BST
VEXT
Symbol
V
IN
, V
CC
V
SW
Value
−0.3 to 100
−1 to 100
−10 to 100
−0.3 to 6
−0.3 to 80
−0.3 to 6.0
−0.3 to 0.3
2000
1500
−40 to +125
−40 to +125
+150
−55 to +150
V
V
V
V
V
V
°C
°C
°C
°C
Unit
V
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. THERMAL INFORMATION
HS FET Junction−to−case thermal resistance (Note 1)
LS FET Junction−to−case thermal resistance (Note 1)
mC
Junction−to−Ambient thermal resistance (Note 1)
Junction−to−case characterization parameter
R
qJA−HS
R
qJA−LS
R
qJA−Controller
Y
JC
25
26
27
0.5
°C/W
1. R
θJC
thermal resistance is obtained by simulating a cold plate test on the exposed power pad. No specific JEDEC standard test exists, but
a close description can be found in the ANSI SEMI standard G30−88.
Table 4. RECOMMENDED OPERATING CONDITIONS
(over operating free−air, unless otherwise noted)
Rating
Power Supply to PGND
VSW to PGND
BST to SW
VEXT to PGND
AGND to PGND
All other pins
Symbol
V
IN
, V
CC
VSW
BST
VEXT
AGND
Value
−0.3 to 80
−1 to 80
−0.6 to 5.5
−0.3 to 60
0
−0.3 to 5.5
Unit
V
V
V
V
V
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
NCP4060A
Table 5. ELECTRICAL CHARACTERISTICS
(−40°C < T
J
= T
A
< +125°C, V
IN
= V
CC
= 48 V, for min/max values unless otherwise
noted, T
A
= T
J
= +25°C for typical values, VB = VDD, VEXT = 0 V)
Parameter
POWER SUPPLY
V
IN
Operation Voltage
V
CC
Operation Voltage
VB Output Voltage
VB Dropout voltage
VB Current Limit
VDD UVLO Threshold (Rising)
VDD UVLO Hysteresis
V
CC
Quiescent Current
Shutdown Supply Current
EN = H, COMP = L, PG open;
VIN = VCC = 48 V, Fsw = 300 kHz
EN = 1 V; VIN = VCC = 48 V;
PG open
EN = 0 V; VIN = VCC = 48 V;
PG open
FEEDBACK VOLTAGE
FB input voltage
VFB
T
J
= 25°C, 16 V
≤
V
CC
≤
80 V
−40°C
≤
T
J
≤
125°C;
16 V
≤
V
CC
≤
80 V
Feedback Input Bias Current
ERROR AMPLIFIER
Open Loop DC Gain (GBD)
Open Loop Unity Gain Bandwidth
Open Loop Phase Margin
Slew Rate
COMP Clamp Voltage, High
Output Source Current
Output Sink Current
CURRENT LIMIT
Low−side R
DS(on)
/ISET
Low−side ISET Current Source
Temperature Coefficient
Low−side OCP switch−over threshold
Low−side Fixed OCP threshold
Low−side programmable OCP range
LS OCP Blanking time
High−side OCP
PWM
Minimum OFF−Time
Minimum duty cycle
Minimum ON−Time
PWM Ramp Amplitude
PWM Ramp Offset
16 V
≤
V
IN
≤
80 V
VCOMP < PWM Ramp Offset
Voltage
330
8
50
V
IN
/30
0.18
ns
%
ns
V
V
LS_OCPth
LS_OCPth
LS_Tblnk
HS_OCP
R
DS(on)
/ISET
TC_LS_ISET
Guaranteed by design
Guaranteed by design
Guaranteed by design
Guaranteed by design
Guaranteed by characterization
150
2xLS_OCP
Guaranteed by characterization,
T
A
= 25°C
440
+0.36
0.6
150
<600
W/A
%/°C
V
mV
mV
ns
A
VFB = 0 V
VFB = 1.5 V
6
17
COMP pin to GND = 10 pF
F0dB, EA
60
85
24
60
2.5
3.4
dB
MHz
deg
V/ms
V
mA
mA
IFB
VFB = 1.25 V
1.24
1.237
1.25
1.25
100
1.26
1.262
120
nA
V
V
IN
V
CC
VB
IB = 5 mA
V
CC
= 48 V
4.3
16
16
5.0
5.25
0.6
117
4.6
0.4
5.5
700
160
10
4.8
80
80
5.6
1.8
V
V
V
V
mA
V
V
mA
mA
mA
Symbol
Test Conditions
Min
Typ
Max
Units
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